diff --git a/.gitignore b/.gitignore index 13751d2a..3233f591 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,3 @@ -./rtl/obj_dir/debug.txt +./rtl/obj_dir/ +./rtl/.* +.* diff --git a/rtl/.DS_Store b/rtl/.DS_Store index b08a3367..9e68d61a 100644 Binary files a/rtl/.DS_Store and b/rtl/.DS_Store differ diff --git a/rtl/._VX_back_end.v b/rtl/._VX_back_end.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/._VX_back_end.v and /dev/null differ diff --git a/rtl/._VX_generic_register.v b/rtl/._VX_generic_register.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/._VX_generic_register.v and /dev/null differ diff --git a/rtl/._VX_gpr.v b/rtl/._VX_gpr.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/._VX_gpr.v and /dev/null differ diff --git a/rtl/._VX_gpr_syn.v b/rtl/._VX_gpr_syn.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/._VX_gpr_syn.v and /dev/null differ diff --git a/rtl/._VX_gpr_wrapper.v b/rtl/._VX_gpr_wrapper.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/._VX_gpr_wrapper.v and /dev/null differ diff --git a/rtl/Makefile b/rtl/Makefile index abe1639e..55b20d07 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -1,4 +1,3 @@ - all: RUNFILE @@ -9,5 +8,4 @@ RUNFILE: VERILATOR (cd obj_dir && make -j -f VVortex.mk) clean: - rm ./obj_dir/* - + rm ./obj_dir/* \ No newline at end of file diff --git a/rtl/VX_csr_handler.v b/rtl/VX_csr_handler.v index e136ce3b..afa21b8e 100644 --- a/rtl/VX_csr_handler.v +++ b/rtl/VX_csr_handler.v @@ -46,14 +46,13 @@ module VX_csr_handler ( end end - + reg[11:0] data_read; always @(posedge clk) begin if(in_mem_is_csr) begin csr[in_mem_csr_address] <= in_mem_csr_result[11:0]; end end - reg[11:0] data_read; always @(negedge clk) begin data_read <= csr[decode_csr_address]; end diff --git a/rtl/VX_define.h b/rtl/VX_define.h index 2273b35e..8b20e1c6 100644 --- a/rtl/VX_define.h +++ b/rtl/VX_define.h @@ -1,5 +1,3 @@ - - #define NT 4 #define NT_M1 (NT-1) @@ -97,11 +95,4 @@ // COLORS #define GREEN "\033[32m" #define RED "\033[31m" -#define DEFAULT "\033[39m" - - - - - - - +#define DEFAULT "\033[39m" \ No newline at end of file diff --git a/rtl/VX_gpr.v b/rtl/VX_gpr.v index 7ac9d6ff..c306ede2 100644 --- a/rtl/VX_gpr.v +++ b/rtl/VX_gpr.v @@ -11,12 +11,40 @@ module VX_gpr ( output reg[`NT_M1:0][31:0] out_b_reg_data ); - - logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits] - wire write_enable; assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0)); + // USING RAM blocks + // First RAM + byte_enabled_simple_dual_port_ram first_ram( + .we (write_enable), + .clk (clk), + .waddr(VX_writeback_inter.rd), + .raddr(VX_gpr_read.rs1), + .be (VX_writeback_inter.wb_valid), + .wdata(VX_writeback_inter.write_data), + .q (out_a_reg_data) + ); + + // Second RAM block + byte_enabled_simple_dual_port_ram second_ram( + .we (write_enable), + .clk (clk), + .waddr(VX_writeback_inter.rd), + .raddr(VX_gpr_read.rs2), + .be (VX_writeback_inter.wb_valid), + .wdata(VX_writeback_inter.write_data), + .q (out_b_reg_data) + ); + + + + + // logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits] + + // wire write_enable; + + // assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0)); // assign read_enable = valid_request; // // Using Registers @@ -35,44 +63,4 @@ module VX_gpr ( // end - - - // USING RAM blocks - - // First RAM - integer thread_index_1; - always_ff@(posedge clk) - begin - if (write_enable) begin - for (thread_index_1 = 0; thread_index_1 <= `NT_M1; thread_index_1 = thread_index_1 + 1) begin - if (VX_writeback_inter.wb_valid[thread_index_1]) begin - gpr[VX_writeback_inter.rd][thread_index_1] <= VX_writeback_inter.write_data[thread_index_1]; - end - end - end - end - - always @(negedge clk) begin - out_a_reg_data <= gpr[VX_gpr_read.rs1]; - end - - - // Second RAM - integer thread_index_2; - always_ff@(posedge clk) - begin - if (write_enable) begin - for (thread_index_2 = 0; thread_index_2 <= `NT_M1; thread_index_2 = thread_index_2 + 1) begin - if (VX_writeback_inter.wb_valid[thread_index_2]) begin - gpr[VX_writeback_inter.rd][thread_index_2] <= VX_writeback_inter.write_data[thread_index_2]; - end - end - end - end - - always @(negedge clk) begin - out_b_reg_data <= gpr[VX_gpr_read.rs2]; - end - - endmodule \ No newline at end of file diff --git a/rtl/VX_gpr_syn.v b/rtl/VX_gpr_syn.v index 6b53490a..2a0e088d 100644 --- a/rtl/VX_gpr_syn.v +++ b/rtl/VX_gpr_syn.v @@ -47,10 +47,10 @@ module VX_gpr_syn ( // wire[`NT_M1:0][31:0] jal_data; // genvar index; - // for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC; + // for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = 0; - // assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num]; + // assign out_a_reg_data = 0 ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num]; // assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num]; @@ -63,7 +63,7 @@ module VX_gpr_syn ( // wire curr_warp_zero = VX_gpr_read.warp_num == 0; // wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0); - // wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0); + // wire real_zero_isclone = 0; // wire write_register = (VX_writeback_inter.wb != 2'h0) ? (1'b1) : (1'b0); @@ -76,10 +76,10 @@ module VX_gpr_syn ( // .in_src1 (VX_gpr_read.rs1), // .in_src2 (VX_gpr_read.rs2), // .in_is_clone (real_zero_isclone), - // .in_src1_fwd (VX_fwd_rsp.src1_fwd), - // .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data), - // .in_src2_fwd (VX_fwd_rsp.src2_fwd), - // .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data), + // .in_src1_fwd (0), + // .in_src1_fwd_data (0), + // .in_src2_fwd (0), + // .in_src2_fwd_data (0), // .in_write_register(write_register), // .in_write_data (VX_writeback_inter.write_data), // .out_a_reg_data (temp_a_reg_data[0]), @@ -93,8 +93,8 @@ module VX_gpr_syn ( // for (r = 1; r < `NW; r = r + 1) begin // wire context_glob_valid = (VX_writeback_inter.wb_warp_num == r); // wire curr_warp_glob = VX_gpr_read.warp_num == r; - // wire real_wspawn = VX_gpr_wspawn.is_wspawn && (VX_gpr_wspawn.which_wspawn == r); - // wire real_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == r); + // wire real_wspawn = 0; + // wire real_isclone = 0; // VX_context_slave VX_Context_one( // .clk (clk), // .in_warp (curr_warp_glob), @@ -104,10 +104,10 @@ module VX_gpr_syn ( // .in_src1 (VX_gpr_read.rs1), // .in_src2 (VX_gpr_read.rs2), // .in_is_clone (real_isclone), - // .in_src1_fwd (VX_fwd_rsp.src1_fwd), - // .in_src1_fwd_data (VX_fwd_rsp.src1_fwd_data), - // .in_src2_fwd (VX_fwd_rsp.src2_fwd), - // .in_src2_fwd_data (VX_fwd_rsp.src2_fwd_data), + // .in_src1_fwd (0), + // .in_src1_fwd_data (0), + // .in_src2_fwd (0), + // .in_src2_fwd_data (0), // .in_write_register(write_register), // .in_write_data (VX_writeback_inter.write_data), // .in_wspawn_regs (w0_t0_registers), @@ -149,25 +149,6 @@ module VX_gpr_syn ( assign out_gpr_stall = 0; - // // WSPAWN FSM - // reg[3:0] wspawn_state; - // VX_gpr_read_inter VX_wspawn_gpr_read(); - // VX_wb_inter VX_wspawn_wb_inter(); - - // VX_wspawn_gpr_read.rs1 - - // always @(posedge clk) begin - // if ((in_wspawn) && wspawn_state == 0) begin - // wspawn_state <= 10; - // end else if (wspawn_state == 1) begin - // wspawn_state <= 0; - // end else if (wspawn_state > 0) begin - // wspawn_state <= wspawn_state - 1; - // end - // end - // assign out_gpr_stall = ((wspawn_state == 0) && VX_gpr_wspawn.is_wspawn) || (VX_gpr_wspawn.is_wspawn > 1);; - - endmodule diff --git a/rtl/Vortex.qsf b/rtl/Vortex.qsf deleted file mode 100644 index ffec91eb..00000000 --- a/rtl/Vortex.qsf +++ /dev/null @@ -1,47 +0,0 @@ -set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name TOP_LEVEL_ENTITY Vortex -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:29 MAY 12, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition" -set_global_assignment -name VERILOG_FILE ./Vortex.v -set_global_assignment -name VERILOG_FILE ./VX_alu.v -set_global_assignment -name VERILOG_FILE ./VX_context.v -set_global_assignment -name VERILOG_FILE ./VX_context_slave.v -set_global_assignment -name VERILOG_FILE ./VX_csr_handler.v -set_global_assignment -name VERILOG_FILE ./VX_d_e_reg.v -set_global_assignment -name VERILOG_FILE ./VX_decode.v -set_global_assignment -name VERILOG_FILE ./VX_define.v -set_global_assignment -name VERILOG_FILE ./VX_e_m_reg.v -set_global_assignment -name VERILOG_FILE ./VX_execute.v -set_global_assignment -name VERILOG_FILE ./VX_f_d_reg.v -set_global_assignment -name VERILOG_FILE ./VX_fetch.v -set_global_assignment -name VERILOG_FILE ./VX_forwarding.v -set_global_assignment -name VERILOG_FILE ./VX_m_w_reg.v -set_global_assignment -name VERILOG_FILE ./VX_memory.v -set_global_assignment -name VERILOG_FILE ./VX_register_file.v -set_global_assignment -name VERILOG_FILE ./VX_register_file_master_slave.v -set_global_assignment -name VERILOG_FILE ./VX_register_file_slave.v -set_global_assignment -name VERILOG_FILE ./VX_warp.v -set_global_assignment -name VERILOG_FILE ./VX_writeback.v -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name DEVICE 10AX115U3F45I2SG -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4 -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 50000 -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SDC_FILE clk_const.sdc -set_global_assignment -name ALLOW_REGISTER_RETIMING OFF -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -set_global_assignment -name AUTO_ROM_RECOGNITION OFF -set_global_assignment -name AUTO_RAM_RECOGNITION OFF -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS ON -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF -set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON -set_instance_assignment -name PARTITION_COLOUR 4288217044 -to Vortex -entity Vortex diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v new file mode 100644 index 00000000..ff9a4776 --- /dev/null +++ b/rtl/byte_enabled_simple_dual_port_ram.v @@ -0,0 +1,33 @@ + +`include "VX_define.v" + + +module byte_enabled_simple_dual_port_ram +( + input we, clk, + input wire[4:0] waddr, raddr, + input wire[`NT_M1:0] be, + input wire[`NT_M1:0][31:0] wdata, + output reg[`NT_M1:0][31:0] q +); + + // Thread Byte Bit + logic [`NT_M1:0][3:0][7:0] GPR[31:0]; + always_ff@(posedge clk) begin + if(we) begin + integer thread_ind; + for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin + if(be[thread_ind]) GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0]; + if(be[thread_ind]) GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8]; + if(be[thread_ind]) GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16]; + if(be[thread_ind]) GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24]; + end + end + end + + + always_ff@(negedge clk) begin + q <= GPR[raddr]; + end + +endmodule \ No newline at end of file diff --git a/rtl/interfaces/._VX_branch_response_inter.v b/rtl/interfaces/._VX_branch_response_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_branch_response_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_csr_write_request_inter.v b/rtl/interfaces/._VX_csr_write_request_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_csr_write_request_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_dcache_request_inter.v b/rtl/interfaces/._VX_dcache_request_inter.v deleted file mode 100644 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a/rtl/interfaces/._VX_forward_mem_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_forward_reqeust_inter.v b/rtl/interfaces/._VX_forward_reqeust_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_forward_reqeust_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_forward_response_inter.v b/rtl/interfaces/._VX_forward_response_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_forward_response_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_forward_wb_inter.v b/rtl/interfaces/._VX_forward_wb_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_forward_wb_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_frE_to_bckE_req_inter.v b/rtl/interfaces/._VX_frE_to_bckE_req_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_frE_to_bckE_req_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_gpr_clone_inter.v b/rtl/interfaces/._VX_gpr_clone_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_gpr_clone_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_gpr_jal_inter.v b/rtl/interfaces/._VX_gpr_jal_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_gpr_jal_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_gpr_read_inter.v b/rtl/interfaces/._VX_gpr_read_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_gpr_read_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_gpr_wspawn_inter.v b/rtl/interfaces/._VX_gpr_wspawn_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_gpr_wspawn_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_icache_request_inter.v b/rtl/interfaces/._VX_icache_request_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_icache_request_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_icache_response_inter.v b/rtl/interfaces/._VX_icache_response_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_icache_response_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_inst_mem_wb_inter.v b/rtl/interfaces/._VX_inst_mem_wb_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_inst_mem_wb_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_inst_meta_inter.v b/rtl/interfaces/._VX_inst_meta_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_inst_meta_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_jal_response_inter.v b/rtl/interfaces/._VX_jal_response_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_jal_response_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_mem_req_inter.v b/rtl/interfaces/._VX_mem_req_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_mem_req_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_mw_wb_inter.v b/rtl/interfaces/._VX_mw_wb_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_mw_wb_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_warp_ctl_inter.v b/rtl/interfaces/._VX_warp_ctl_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_warp_ctl_inter.v and /dev/null differ diff --git a/rtl/interfaces/._VX_wb_inter.v b/rtl/interfaces/._VX_wb_inter.v deleted file mode 100644 index e28521c3..00000000 Binary files a/rtl/interfaces/._VX_wb_inter.v and /dev/null differ diff --git a/rtl/obj_dir/VVX_gpr_syn.cpp b/rtl/obj_dir/VVX_gpr_syn.cpp deleted file mode 100644 index 31843a5e..00000000 --- a/rtl/obj_dir/VVX_gpr_syn.cpp +++ /dev/null @@ -1,1695 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See VVX_gpr_syn.h for the primary calling header - -#include "VVX_gpr_syn.h" -#include "VVX_gpr_syn__Syms.h" - - -//-------------------- -// STATIC VARIABLES - - -//-------------------- - -VL_CTOR_IMP(VVX_gpr_syn) { - VVX_gpr_syn__Syms* __restrict vlSymsp = __VlSymsp = new VVX_gpr_syn__Syms(this, name()); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Reset internal values - - // Reset structure values - _ctor_var_reset(); -} - -void VVX_gpr_syn::__Vconfigure(VVX_gpr_syn__Syms* vlSymsp, bool first) { - if (0 && first) {} // Prevent unused - this->__VlSymsp = vlSymsp; -} - -VVX_gpr_syn::~VVX_gpr_syn() { - delete __VlSymsp; __VlSymsp=NULL; -} - -//-------------------- - - -void VVX_gpr_syn::eval() { - VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_gpr_syn::eval\n"); ); - VVX_gpr_syn__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -#ifdef VL_DEBUG - // Debug assertions - _eval_debug_assertions(); -#endif // VL_DEBUG - // Initialize - if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); - // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; - do { - VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); - _eval(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) { - // About to fail, so enable debug to see what's not settling. - // Note you must run make with OPT=-DVL_DEBUG for debug prints. - int __Vsaved_debug = Verilated::debug(); - Verilated::debug(1); - __Vchange = _change_request(vlSymsp); - Verilated::debug(__Vsaved_debug); - VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); - } else { - __Vchange = _change_request(vlSymsp); - } - } while (VL_UNLIKELY(__Vchange)); -} - -void VVX_gpr_syn::_eval_initial_loop(VVX_gpr_syn__Syms* __restrict vlSymsp) { - vlSymsp->__Vm_didInit = true; - _eval_initial(vlSymsp); - // Evaluate till stable - int __VclockLoop = 0; - QData __Vchange = 1; - do { - _eval_settle(vlSymsp); - _eval(vlSymsp); - if (VL_UNLIKELY(++__VclockLoop > 100)) { - // About to fail, so enable debug to see what's not settling. - // Note you must run make with OPT=-DVL_DEBUG for debug prints. - int __Vsaved_debug = Verilated::debug(); - Verilated::debug(1); - __Vchange = _change_request(vlSymsp); - Verilated::debug(__Vsaved_debug); - VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); - } else { - __Vchange = _change_request(vlSymsp); - } - } while (VL_UNLIKELY(__Vchange)); -} - -//-------------------- -// Internal Methods - -void VVX_gpr_syn::_initial__TOP__1(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_initial__TOP__1\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // INITIAL at VX_gpr_syn.v:149 - vlTOPp->out_gpr_stall = 0U; -} - -VL_INLINE_OPT void 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VL_SIG(__Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3,31,0); - // Body - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 = 0U; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 = 0U; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs1][3U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][0U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][1U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][2U]; - vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [vlTOPp->rs2][3U]; - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYS at VX_gpr.v:24 - if (vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable) { - if ((1U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->write_data[0U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlTOPp->rd; - } - if ((2U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->write_data[1U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlTOPp->rd; - } - if ((4U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->write_data[2U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlTOPp->rd; - } - if ((8U & (IData)(vlTOPp->wb_valid))) { - __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->write_data[3U]; - __Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlTOPp->rd; - } - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3); - } - // ALWAYSPOST at VX_gpr.v:29 - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2); - } - if (__Vdlyvset__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3); - } - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1cU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1dU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1eU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1fU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1cU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1dU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1eU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1fU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x18U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x19U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1aU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1bU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x18U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x19U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1aU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1bU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x14U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x15U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x16U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x17U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x14U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x15U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x16U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x17U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x10U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x11U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x12U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x13U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x10U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x11U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x12U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x13U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xcU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xdU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xeU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xfU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xcU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xdU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xeU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xfU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[8U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[9U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xaU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xbU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[8U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[9U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xaU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xbU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[4U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[5U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[6U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[7U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[4U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[5U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[6U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[7U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U]; -} - -void VVX_gpr_syn::_settle__TOP__3(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_settle__TOP__3\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable - = ((0U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable - = ((1U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable - = ((2U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable - = ((3U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable - = ((4U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable - = ((5U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable - = ((6U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable - = ((7U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[1U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[2U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[3U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[4U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[5U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[6U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[7U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[4U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[5U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[6U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[7U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[8U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[9U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xaU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xbU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[8U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[9U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xaU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xbU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xcU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xdU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xeU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0xfU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xcU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xdU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xeU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0xfU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x10U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x11U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x12U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x13U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x10U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x11U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x12U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x13U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x14U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x15U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x16U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x17U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x14U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x15U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x16U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x17U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x18U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x19U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1aU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1bU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x18U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x19U] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1aU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1bU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1cU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1dU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1eU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[0x1fU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1cU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1dU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1eU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U]; - vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[0x1fU] - = vlTOPp->VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U]; - vlTOPp->out_b_reg_data[0U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(1U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[1U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(2U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(1U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[2U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(3U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(2U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[3U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(4U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(3U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[0U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(1U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[1U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(2U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(1U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[2U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(3U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(2U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[3U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(4U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(3U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); -} - -VL_INLINE_OPT void VVX_gpr_syn::_combo__TOP__4(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_combo__TOP__4\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable - = ((7U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable - = ((6U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable - = ((5U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable - = ((4U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable - = ((3U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable - = ((2U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable - = ((1U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable - = ((0U == (IData)(vlTOPp->wb_warp_num)) & ( - (0U - != (IData)(vlTOPp->wb)) - & (0U - != (IData)(vlTOPp->rd)))); - vlTOPp->out_a_reg_data[0U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(1U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[1U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(2U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(1U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[2U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(3U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(2U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_a_reg_data[3U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(4U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_a_reg_data[ - ((IData)(3U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[0U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(1U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[1U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(2U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(1U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[2U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(3U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(2U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); - vlTOPp->out_b_reg_data[3U] = (((0U == (0x1fU & - ((IData)(vlTOPp->warp_num) - << 7U))) - ? 0U : (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(4U) - + (0x1cU - & ((IData)(vlTOPp->warp_num) - << 2U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->warp_num) - << 7U))))) - | (vlTOPp->VX_gpr_wrapper__DOT__temp_b_reg_data[ - ((IData)(3U) + - (0x1cU & ((IData)(vlTOPp->warp_num) - << 2U)))] - >> (0x1fU & ((IData)(vlTOPp->warp_num) - << 7U)))); -} - -void VVX_gpr_syn::_eval(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_eval\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { - vlTOPp->_sequent__TOP__2(vlSymsp); - } - vlTOPp->_combo__TOP__4(vlSymsp); - // Final - vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; -} - -void VVX_gpr_syn::_eval_initial(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_eval_initial\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_initial__TOP__1(vlSymsp); - vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; -} - -void VVX_gpr_syn::final() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::final\n"); ); - // Variables - VVX_gpr_syn__Syms* __restrict vlSymsp = this->__VlSymsp; - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; -} - -void VVX_gpr_syn::_eval_settle(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_eval_settle\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - vlTOPp->_settle__TOP__3(vlSymsp); -} - -VL_INLINE_OPT QData VVX_gpr_syn::_change_request(VVX_gpr_syn__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_change_request\n"); ); - VVX_gpr_syn* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; - // Body - // Change detection - QData __req = false; // Logically a bool - return __req; -} - -#ifdef VL_DEBUG -void VVX_gpr_syn::_eval_debug_assertions() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_eval_debug_assertions\n"); ); - // Body - if (VL_UNLIKELY((clk & 0xfeU))) { - Verilated::overWidthError("clk");} - if (VL_UNLIKELY((rs1 & 0xe0U))) { - Verilated::overWidthError("rs1");} - if (VL_UNLIKELY((rs2 & 0xe0U))) { - Verilated::overWidthError("rs2");} - if (VL_UNLIKELY((warp_num & 0xf0U))) { - Verilated::overWidthError("warp_num");} - if (VL_UNLIKELY((rd & 0xe0U))) { - Verilated::overWidthError("rd");} - if (VL_UNLIKELY((wb & 0xfcU))) { - Verilated::overWidthError("wb");} - if (VL_UNLIKELY((wb_valid & 0xf0U))) { - Verilated::overWidthError("wb_valid");} - if (VL_UNLIKELY((wb_warp_num & 0xf0U))) { - Verilated::overWidthError("wb_warp_num");} -} -#endif // VL_DEBUG - -void VVX_gpr_syn::_ctor_var_reset() { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_gpr_syn::_ctor_var_reset\n"); ); - // Body - clk = VL_RAND_RESET_I(1); - rs1 = VL_RAND_RESET_I(5); - rs2 = VL_RAND_RESET_I(5); - warp_num = VL_RAND_RESET_I(4); - VL_RAND_RESET_W(128,write_data); - rd = VL_RAND_RESET_I(5); - wb = VL_RAND_RESET_I(2); - wb_valid = VL_RAND_RESET_I(4); - wb_warp_num = VL_RAND_RESET_I(4); - VL_RAND_RESET_W(128,out_a_reg_data); - VL_RAND_RESET_W(128,out_b_reg_data); - out_gpr_stall = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(1024,VX_gpr_wrapper__DOT__temp_a_reg_data); - VL_RAND_RESET_W(1024,VX_gpr_wrapper__DOT__temp_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} - VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); -} diff --git a/rtl/obj_dir/VVX_gpr_syn.h b/rtl/obj_dir/VVX_gpr_syn.h deleted file mode 100644 index 67deebe0..00000000 --- a/rtl/obj_dir/VVX_gpr_syn.h +++ /dev/null @@ -1,129 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Primary design header -// -// This header should be included by all source files instantiating the design. -// The class here is then constructed to instantiate the design. -// See the Verilator manual for examples. - -#ifndef _VVX_gpr_syn_H_ -#define _VVX_gpr_syn_H_ - -#include "verilated.h" - -class VVX_gpr_syn__Syms; - -//---------- - -VL_MODULE(VVX_gpr_syn) { - public: - - // PORTS - // The application code writes and reads these signals to - // propagate new values into/out from the Verilated model. - // Begin mtask footprint all: - VL_IN8(clk,0,0); - VL_IN8(rs1,4,0); - VL_IN8(rs2,4,0); - VL_IN8(warp_num,3,0); - VL_IN8(rd,4,0); - VL_IN8(wb,1,0); - VL_IN8(wb_valid,3,0); - VL_IN8(wb_warp_num,3,0); - VL_OUT8(out_gpr_stall,0,0); - VL_INW(write_data,127,0,4); - VL_OUTW(out_a_reg_data,127,0,4); - VL_OUTW(out_b_reg_data,127,0,4); - - // LOCAL SIGNALS - // Internals; generally not touched by application code - // Begin mtask footprint all: - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIG8(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0); - VL_SIGW(VX_gpr_wrapper__DOT__temp_a_reg_data,1023,0,32); - VL_SIGW(VX_gpr_wrapper__DOT__temp_b_reg_data,1023,0,32); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT__genblk1__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - - // LOCAL VARIABLES - // Internals; generally not touched by application code - // Begin mtask footprint all: - VL_SIG8(__Vclklast__TOP__clk,0,0); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(VX_gpr_wrapper__DOT____Vcellout__genblk1__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - - // INTERNAL VARIABLES - // Internals; generally not touched by application code - VVX_gpr_syn__Syms* __VlSymsp; // Symbol table - - // PARAMETERS - // Parameters marked /*verilator public*/ for use by application code - - // CONSTRUCTORS - private: - VL_UNCOPYABLE(VVX_gpr_syn); ///< Copying not allowed - public: - /// Construct the model; called by application code - /// The special name may be used to make a wrapper with a - /// single model invisible with respect to DPI scope names. - VVX_gpr_syn(const char* name="TOP"); - /// Destroy the model; called (often implicitly) by application code - ~VVX_gpr_syn(); - - // API METHODS - /// Evaluate the model. Application must call when inputs change. - void eval(); - /// Simulation complete, run final blocks. Application must call on completion. - void final(); - - // INTERNAL METHODS - private: - static void _eval_initial_loop(VVX_gpr_syn__Syms* __restrict vlSymsp); - public: - void __Vconfigure(VVX_gpr_syn__Syms* symsp, bool first); - private: - static QData _change_request(VVX_gpr_syn__Syms* __restrict vlSymsp); - public: - static void _combo__TOP__4(VVX_gpr_syn__Syms* __restrict vlSymsp); - private: - void _ctor_var_reset() VL_ATTR_COLD; - public: - static void _eval(VVX_gpr_syn__Syms* __restrict vlSymsp); - private: -#ifdef VL_DEBUG - void _eval_debug_assertions(); -#endif // VL_DEBUG - public: - static void _eval_initial(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD; - static void _eval_settle(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD; - static void _initial__TOP__1(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD; - static void _sequent__TOP__2(VVX_gpr_syn__Syms* __restrict vlSymsp); - static void _settle__TOP__3(VVX_gpr_syn__Syms* __restrict vlSymsp) VL_ATTR_COLD; -} VL_ATTR_ALIGNED(128); - -#endif // guard diff --git a/rtl/obj_dir/VVX_gpr_syn.mk b/rtl/obj_dir/VVX_gpr_syn.mk deleted file mode 100644 index 7d5ee19e..00000000 --- a/rtl/obj_dir/VVX_gpr_syn.mk +++ /dev/null @@ -1,53 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable -# -# Execute this makefile from the object directory: -# make -f VVX_gpr_syn.mk - -default: VVX_gpr_syn__ALL.a - -### Constants... -# Perl executable (from $PERL) -PERL = perl -# Path to Verilator kit (from $VERILATOR_ROOT) -VERILATOR_ROOT = /usr/local/share/verilator -# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) -SYSTEMC_INCLUDE ?= -# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) -SYSTEMC_LIBDIR ?= - -### Switches... -# SystemC output mode? 0/1 (from --sc) -VM_SC = 0 -# Legacy or SystemC output mode? 0/1 (from --sc) -VM_SP_OR_SC = $(VM_SC) -# Deprecated -VM_PCLI = 1 -# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) -VM_SC_TARGET_ARCH = linux - -### Vars... -# Design prefix (from --prefix) -VM_PREFIX = VVX_gpr_syn -# Module prefix (from --prefix) -VM_MODPREFIX = VVX_gpr_syn -# User CFLAGS (from -CFLAGS on Verilator command line) -VM_USER_CFLAGS = \ - -# User LDLIBS (from -LDFLAGS on Verilator command line) -VM_USER_LDLIBS = \ - -# User .cpp files (from .cpp's on Verilator command line) -VM_USER_CLASSES = \ - -# User .cpp directories (from .cpp's on Verilator command line) -VM_USER_DIR = \ - - -### Default rules... -# Include list of all generated classes -include VVX_gpr_syn_classes.mk -# Include global rules -include $(VERILATOR_ROOT)/include/verilated.mk - -# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVX_gpr_syn__Syms.cpp b/rtl/obj_dir/VVX_gpr_syn__Syms.cpp deleted file mode 100644 index e62e04b5..00000000 --- a/rtl/obj_dir/VVX_gpr_syn__Syms.cpp +++ /dev/null @@ -1,19 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table implementation internals - -#include "VVX_gpr_syn__Syms.h" -#include "VVX_gpr_syn.h" - -// FUNCTIONS -VVX_gpr_syn__Syms::VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep) - // Setup locals - : __Vm_namep(namep) - , __Vm_didInit(false) - // Setup submodule names -{ - // Pointer to top level - TOPp = topp; - // Setup each module's pointers to their submodules - // Setup each module's pointer back to symbol table (for public functions) - TOPp->__Vconfigure(this, true); -} diff --git a/rtl/obj_dir/VVX_gpr_syn__Syms.h b/rtl/obj_dir/VVX_gpr_syn__Syms.h deleted file mode 100644 index 9c07ff20..00000000 --- a/rtl/obj_dir/VVX_gpr_syn__Syms.h +++ /dev/null @@ -1,35 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table internal header -// -// Internal details; most calling programs do not need this header, -// unless using verilator public meta comments. - -#ifndef _VVX_gpr_syn__Syms_H_ -#define _VVX_gpr_syn__Syms_H_ - -#include "verilated.h" - -// INCLUDE MODULE CLASSES -#include "VVX_gpr_syn.h" - -// SYMS CLASS -class VVX_gpr_syn__Syms : public VerilatedSyms { - public: - - // LOCAL STATE - const char* __Vm_namep; - bool __Vm_didInit; - - // SUBCELL STATE - VVX_gpr_syn* TOPp; - - // CREATORS - VVX_gpr_syn__Syms(VVX_gpr_syn* topp, const char* namep); - ~VVX_gpr_syn__Syms() {} - - // METHODS - inline const char* name() { return __Vm_namep; } - -} VL_ATTR_ALIGNED(64); - -#endif // guard diff --git a/rtl/obj_dir/VVX_gpr_syn__ver.d b/rtl/obj_dir/VVX_gpr_syn__ver.d deleted file mode 100644 index 956a62b4..00000000 --- a/rtl/obj_dir/VVX_gpr_syn__ver.d +++ /dev/null @@ -1 +0,0 @@ -obj_dir/VVX_gpr_syn.cpp obj_dir/VVX_gpr_syn.h obj_dir/VVX_gpr_syn.mk obj_dir/VVX_gpr_syn__Syms.cpp obj_dir/VVX_gpr_syn__Syms.h obj_dir/VVX_gpr_syn__ver.d obj_dir/VVX_gpr_syn_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_define.v VX_gpr.v VX_gpr_syn.v interfaces/../VX_define.v interfaces/VX_gpr_read_inter.v interfaces/VX_wb_inter.v diff --git a/rtl/obj_dir/VVX_gpr_syn__verFiles.dat b/rtl/obj_dir/VVX_gpr_syn__verFiles.dat deleted file mode 100644 index 29b32430..00000000 --- a/rtl/obj_dir/VVX_gpr_syn__verFiles.dat +++ /dev/null @@ -1,17 +0,0 @@ -# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. -C "VX_gpr_syn.v -cc -Iinterfaces" -S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin" -S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v" -S 1179 894272 1568146678 0 1568146678 0 "VX_gpr.v" -S 5776 894945 1568156400 0 1568156400 0 "VX_gpr_syn.v" -S 1676 1565244 1567474434 0 1567474434 0 "interfaces/../VX_define.v" -S 193 894834 1568154198 0 1568154198 0 "interfaces/VX_gpr_read_inter.v" -S 273 894835 1568154164 0 1568154164 0 "interfaces/VX_wb_inter.v" -T 103876 895616 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.cpp" -T 6427 894948 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.h" -T 1458 895150 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn.mk" -T 550 894947 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.cpp" -T 789 894946 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__Syms.h" -T 363 895151 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__ver.d" -T 0 0 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn__verFiles.dat" -T 1257 894949 1568156400 0 1568156400 0 "obj_dir/VVX_gpr_syn_classes.mk" diff --git a/rtl/obj_dir/VVX_gpr_syn_classes.mk b/rtl/obj_dir/VVX_gpr_syn_classes.mk deleted file mode 100644 index 69a933be..00000000 --- a/rtl/obj_dir/VVX_gpr_syn_classes.mk +++ /dev/null @@ -1,40 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Make include file with class lists -# -# This file lists generated Verilated files, for including in higher level makefiles. -# See VVX_gpr_syn.mk for the caller. - -### Switches... -# Coverage output mode? 0/1 (from --coverage) -VM_COVERAGE = 0 -# Threaded output mode? 0/1/N threads (from --threads) -VM_THREADS = 0 -# Tracing output mode? 0/1 (from --trace) -VM_TRACE = 0 -# Tracing threadeds output mode? 0/1 (from --trace-fst-thread) -VM_TRACE_THREADED = 0 - -### Object file lists... -# Generated module classes, fast-path, compile with highest optimization -VM_CLASSES_FAST += \ - VVX_gpr_syn \ - -# Generated module classes, non-fast-path, compile with low/medium optimization -VM_CLASSES_SLOW += \ - -# Generated support classes, fast-path, compile with highest optimization -VM_SUPPORT_FAST += \ - -# Generated support classes, non-fast-path, compile with low/medium optimization -VM_SUPPORT_SLOW += \ - VVX_gpr_syn__Syms \ - -# Global classes, need linked once per executable, fast-path, compile with highest optimization -VM_GLOBAL_FAST += \ - verilated \ - -# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization -VM_GLOBAL_SLOW += \ - - -# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex index 2ae7e365..2348e64d 100755 Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp index 3a2153a0..35f6c673 100644 --- a/rtl/obj_dir/VVortex.cpp +++ b/rtl/obj_dir/VVortex.cpp @@ -289,69 +289,69 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { vlSymsp->TOP__Vortex__DOT__VX_dcache_rsp.in_cache_driver_out_data[0U] = vlTOPp->in_cache_driver_out_data[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[4U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[5U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[6U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[7U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[8U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[9U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xaU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xbU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xcU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xdU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xeU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xfU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x10U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x11U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x12U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x13U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x14U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x15U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x16U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x17U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x18U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x19U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1aU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1bU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1cU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1dU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1eU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1fU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__execute_branch_stall = (1U & ((0U != @@ -363,69 +363,69 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value[2U] >> 8U))); vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[4U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[5U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[6U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[7U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[8U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[9U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xaU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xbU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xcU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xdU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xeU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xfU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x10U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x11U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x12U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x13U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x14U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x15U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x16U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x17U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x18U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x19U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1aU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1bU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1cU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1dU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1eU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1fU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] = ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value[1U] << 0x18U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value[0U] @@ -4220,327 +4220,1287 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables // Begin mtask footprint all: - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6,6,0); - VL_SIG8(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6,0,0); - VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7,4,0); - VL_SIG8(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7,6,0); - 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__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0U; + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0U; // ALWAYS at VX_csr_handler.v:50 if ((8U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value[0xeU])) { vlTOPp->Vortex__DOT__vx_csr_handler__DOT____Vlvbound1 @@ -4568,1021 +5528,4245 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:44 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v0 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v1 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v2 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYS at VX_gpr.v:62 + // ALWAYS at byte_enabled_simple_dual_port_ram.v:16 if (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable) { if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4 = 0U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 = 0U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 = 8U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 = 0x10U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x10U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[0U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = 0x18U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5 = 0x20U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 = 0x20U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 = 0x28U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 = 0x30U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x20U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[1U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = 0x38U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6 = 0x40U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 = 0x40U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x18U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 8U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 = 0x48U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 0x10U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x10U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 = 0x50U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x40U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 + = (0xffU & ((vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + << 8U) | (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[2U] + >> 0x18U))); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = 0x58U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { - __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7 - = vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]; - __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7 = 1U; - __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7 = 0x60U; - __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7 + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0xffU & vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U]); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 = 0x60U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 8U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 = 0x68U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x10U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 = 0x70U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14 + = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] + << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] + >> 0xaU))); + } + if ((0x80U & vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[0U])) { + __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 + = (0xffU & (vlSymsp->TOP__Vortex__DOT__VX_writeback_inter.write_data[3U] + >> 0x18U)); + __Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 1U; + __Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = 0x78U; + __Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15 = (0x1fU & ((vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[2U] << 0x16U) | (vlTOPp->Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value[1U] >> 0xaU))); } } - // ALWAYSPOST at VX_gpr.v:49 - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v0); + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v1); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr__v2); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); } - if 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VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v5); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v6); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); } - // ALWAYSPOST at VX_gpr.v:49 - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v0); + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v1); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v2); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr__v3); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], 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[__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); } - // ALWAYSPOST at VX_gpr.v:49 - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v0); + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v1); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v2); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v3); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v4); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v5); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v6); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); } - // ALWAYSPOST at VX_gpr.v:49 - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v0); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v1); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v2); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v3); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v4); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v5); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v6); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); } - // ALWAYSPOST at VX_gpr.v:49 - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v0); + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v1); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], 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(__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v3); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + 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[__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v4); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], 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VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v6); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + 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[__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], 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__Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v3); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v4); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v5); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v6); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); } - if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7) { - VL_ASSIGNSEL_WIII(32,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7), - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr - [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr__v7); + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], 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VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR__v15); + } + // ALWAYSPOST at byte_enabled_simple_dual_port_ram.v:20 + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v0); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v1); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v2); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v3); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v4); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v5); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v6); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v7); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v8); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v9); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v10); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v11); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v12); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v13); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v14); + } + if (__Vdlyvset__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15), + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR + [__Vdlyvdim0__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15], __Vdlyvval__Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR__v15); } } @@ -5590,343 +9774,343 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__6\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:55 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 9U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x17U)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_gpr.v:73 - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + // ALWAYS at byte_enabled_simple_dual_port_ram.v:29 + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][0U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][1U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][2U]; - vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr + vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U] + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR [(0x1fU & ((vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[2U] << 4U) | (vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value[1U] >> 0x1cU)))][3U]; - // ALWAYS at VX_csr_handler.v:57 + // ALWAYS at VX_csr_handler.v:56 vlTOPp->Vortex__DOT__vx_csr_handler__DOT__data_read = (0xfffU & ((0x300bU >= (0x3fffU & ((IData)(0xcU) * (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)))) @@ -5948,133 +10132,133 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) * (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))))) : 0U)); vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1cU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1dU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1eU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1fU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x18U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x19U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1aU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x1bU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x14U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x15U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x16U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x17U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x10U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x11U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x12U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0x13U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xcU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xdU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xeU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xfU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[8U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[9U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xaU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0xbU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[4U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[5U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[6U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[7U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1cU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1dU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1eU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1fU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x18U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x19U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1aU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x1bU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x14U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x15U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x16U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x17U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x10U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x11U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x12U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0x13U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xcU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xdU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xeU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xfU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[8U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[9U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xaU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0xbU] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[4U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[5U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[6U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[7U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[0U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[0U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[0U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[1U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[1U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[1U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[2U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[2U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[2U]; vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data[3U] - = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data[3U]; + = vlTOPp->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q[3U]; } VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) { @@ -9907,54 +14091,78 @@ void VVortex::_ctor_var_reset() { VL_RAND_RESET_W(1024,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data); VL_RAND_RESET_W(1024,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data); VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data); - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data); - { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); - }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { - VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr[__Vi0]); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); }} Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q); + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[__Vi0]); + }} VL_RAND_RESET_W(490,Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in); VL_RAND_RESET_W(490,Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value); Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h index e5540e5b..5a0b9f75 100644 --- a/rtl/obj_dir/VVortex.h +++ b/rtl/obj_dir/VVortex.h @@ -178,14 +178,24 @@ VL_MODULE(VVortex) { VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__in_valid[4],0,0); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__gpr[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); + }; + struct { + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); }; // LOCAL VARIABLES @@ -206,22 +216,22 @@ VL_MODULE(VVortex) { VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_b_reg_data,127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT____Vcellout__vx_grp_wrapper__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__0__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__1__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__2__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__3__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__4__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__5__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__6__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_b_reg_data,127,0,4); - VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT____Vcellout__genblk2__BRA__7__KET____DOT__vx_gpr__out_a_reg_data,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__first_ram__q,127,0,4); + VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT____Vcellout__second_ram__q,127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16); VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0); diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a index 37718afd..56c5604c 100644 Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o index 4a50053e..a2ecc0e0 100644 Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d index b97a1731..ac1e9ca9 100644 --- a/rtl/obj_dir/VVortex__ver.d +++ b/rtl/obj_dir/VVortex__ver.d @@ -1 +1 @@ -obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v +obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_memory.v VX_warp.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v interfaces//../VX_define.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.v interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_gpr_clone_inter.v interfaces//VX_gpr_jal_inter.v interfaces//VX_gpr_read_inter.v interfaces//VX_gpr_wspawn_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat index c3984f34..95afe370 100644 --- a/rtl/obj_dir/VVortex__verFiles.dat +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -1,73 +1,74 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "--compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3" S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin" -S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v" -S 2767 1703128 1567984522 0 1567984522 0 "VX_back_end.v" -S 1837 1768199 1567984564 0 1567984564 0 "VX_csr_handler.v" -S 12015 891625 1568083962 0 1568083962 0 "VX_decode.v" -S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v" -S 3835 891130 1568052328 0 1568052328 0 "VX_execute.v" -S 5000 892191 1568138876 0 1568138876 0 "VX_fetch.v" -S 6148 1701713 1567982096 0 1567982096 0 "VX_forwarding.v" -S 2701 891626 1568084006 0 1568084006 0 "VX_front_end.v" -S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v" -S 2099 895597 1568160868 0 1568160868 0 "VX_gpr.v" -S 5323 894943 1568156252 0 1568156252 0 "VX_gpr_wrapper.v" -S 2584 1768087 1567983338 0 1567983338 0 "VX_memory.v" -S 1903 893490 1568138384 0 1568138384 0 "VX_warp.v" -S 1597 1704649 1567981924 0 1567981924 0 "VX_writeback.v" -S 4392 1703129 1567985238 0 1567985238 0 "Vortex.v" -S 1676 1565244 1567474434 0 1567474434 0 "interfaces//../VX_define.v" -S 227 894833 1568155500 0 1568155500 0 "interfaces//VX_branch_response_inter.v" -S 212 894856 1568154236 0 1568154236 0 "interfaces//VX_csr_write_request_inter.v" -S 373 894855 1568154234 0 1568154234 0 "interfaces//VX_dcache_request_inter.v" -S 186 894854 1568154230 0 1568154230 0 "interfaces//VX_dcache_response_inter.v" -S 282 894852 1568154224 0 1568154224 0 "interfaces//VX_forward_exe_inter.v" -S 327 894851 1568154222 0 1568154222 0 "interfaces//VX_forward_mem_inter.v" -S 204 894850 1568154218 0 1568154218 0 "interfaces//VX_forward_reqeust_inter.v" -S 273 894849 1568154216 0 1568154216 0 "interfaces//VX_forward_response_inter.v" -S 313 894848 1568154210 0 1568154210 0 "interfaces//VX_forward_wb_inter.v" -S 833 894847 1568154206 0 1568154206 0 "interfaces//VX_frE_to_bckE_req_inter.v" -S 253 894846 1568154204 0 1568154204 0 "interfaces//VX_gpr_clone_inter.v" -S 173 894845 1568154200 0 1568154200 0 "interfaces//VX_gpr_jal_inter.v" -S 193 894834 1568154198 0 1568154198 0 "interfaces//VX_gpr_read_inter.v" -S 293 894844 1568154194 0 1568154194 0 "interfaces//VX_gpr_wspawn_inter.v" -S 159 894843 1568154192 0 1568154192 0 "interfaces//VX_icache_request_inter.v" -S 194 894842 1568154188 0 1568154188 0 "interfaces//VX_icache_response_inter.v" -S 366 894841 1568154186 0 1568154186 0 "interfaces//VX_inst_mem_wb_inter.v" -S 237 894840 1568154182 0 1568154182 0 "interfaces//VX_inst_meta_inter.v" -S 205 894839 1568154180 0 1568154180 0 "interfaces//VX_jal_response_inter.v" -S 557 894838 1568154176 0 1568154176 0 "interfaces//VX_mem_req_inter.v" -S 348 894837 1568154174 0 1568154174 0 "interfaces//VX_mw_wb_inter.v" -S 297 894836 1568154170 0 1568154170 0 "interfaces//VX_warp_ctl_inter.v" -S 273 894835 1568154164 0 1568154164 0 "interfaces//VX_wb_inter.v" -T 768547 894861 1568160870 0 1568160870 0 "obj_dir/VVortex.cpp" -T 22072 894859 1568160870 0 1568160870 0 "obj_dir/VVortex.h" -T 1791 894923 1568160870 0 1568160870 0 "obj_dir/VVortex.mk" -T 914 894911 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.cpp" -T 1029 894910 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_branch_response_inter.h" -T 1210 894907 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp" -T 1135 894906 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_request_inter.h" -T 988 894905 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp" -T 1045 894904 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_dcache_response_inter.h" -T 1059 894909 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp" -T 1142 894908 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h" -T 884 894919 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp" -T 1008 894918 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h" -T 865 894915 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp" -T 987 894914 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_inst_meta_inter.h" -T 885 894917 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.cpp" -T 1005 894916 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_mem_req_inter.h" -T 902 894913 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp" -T 1017 894912 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_warp_ctl_inter.h" -T 825 894921 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.cpp" -T 954 894920 1568160870 0 1568160870 0 "obj_dir/VVortex_VX_wb_inter.h" -T 3499 894858 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.cpp" -T 1855 894857 1568160870 0 1568160870 0 "obj_dir/VVortex__Syms.h" -T 2077 894924 1568160870 0 1568160870 0 "obj_dir/VVortex__ver.d" -T 0 0 1568160870 0 1568160870 0 "obj_dir/VVortex__verFiles.dat" -T 1530 894922 1568160870 0 1568160870 0 "obj_dir/VVortex_classes.mk" -S 1884 891629 1568084068 0 1568084068 0 "pipe_regs//VX_d_e_reg.v" -S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v" -S 751 891628 1568084040 0 1568084040 0 "pipe_regs//VX_f_d_reg.v" -S 688 1573273 1567972184 0 1567972184 0 "pipe_regs//VX_m_w_reg.v" +S 2785 897406 1568177864 0 1568177864 0 "VX_alu.v" +S 2767 897407 1568177864 0 1568177864 0 "VX_back_end.v" +S 1836 897410 1568177864 0 1568177864 0 "VX_csr_handler.v" +S 12015 897411 1568177864 0 1568177864 0 "VX_decode.v" +S 1676 897412 1568177866 0 1568177866 0 "VX_define.v" +S 3835 897413 1568177866 0 1568177866 0 "VX_execute.v" +S 5000 897414 1568177866 0 1568177866 0 "VX_fetch.v" +S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v" +S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v" +S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v" +S 1835 897418 1568177866 0 1568177866 0 "VX_gpr.v" +S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v" +S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v" +S 1903 897425 1568177866 0 1568177866 0 "VX_warp.v" +S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v" +S 4392 897427 1568177868 0 1568177868 0 "Vortex.v" +S 821 897428 1568177868 0 1568177868 0 "byte_enabled_simple_dual_port_ram.v" +S 1676 897412 1568177866 0 1568177866 0 "interfaces//../VX_define.v" +S 227 897429 1568177888 0 1568177888 0 "interfaces//VX_branch_response_inter.v" +S 212 897430 1568177888 0 1568177888 0 "interfaces//VX_csr_write_request_inter.v" +S 373 897431 1568177888 0 1568177888 0 "interfaces//VX_dcache_request_inter.v" +S 186 897432 1568177888 0 1568177888 0 "interfaces//VX_dcache_response_inter.v" +S 282 897434 1568177888 0 1568177888 0 "interfaces//VX_forward_exe_inter.v" +S 327 897435 1568177888 0 1568177888 0 "interfaces//VX_forward_mem_inter.v" +S 204 897436 1568177888 0 1568177888 0 "interfaces//VX_forward_reqeust_inter.v" +S 273 897437 1568177888 0 1568177888 0 "interfaces//VX_forward_response_inter.v" +S 313 897438 1568177888 0 1568177888 0 "interfaces//VX_forward_wb_inter.v" +S 833 897439 1568177888 0 1568177888 0 "interfaces//VX_frE_to_bckE_req_inter.v" +S 253 897441 1568177888 0 1568177888 0 "interfaces//VX_gpr_clone_inter.v" +S 173 897442 1568177888 0 1568177888 0 "interfaces//VX_gpr_jal_inter.v" +S 193 897443 1568177888 0 1568177888 0 "interfaces//VX_gpr_read_inter.v" +S 293 897444 1568177888 0 1568177888 0 "interfaces//VX_gpr_wspawn_inter.v" +S 159 897445 1568177890 0 1568177890 0 "interfaces//VX_icache_request_inter.v" +S 194 897446 1568177890 0 1568177890 0 "interfaces//VX_icache_response_inter.v" +S 366 897447 1568177890 0 1568177890 0 "interfaces//VX_inst_mem_wb_inter.v" +S 237 897448 1568177890 0 1568177890 0 "interfaces//VX_inst_meta_inter.v" +S 205 897449 1568177890 0 1568177890 0 "interfaces//VX_jal_response_inter.v" +S 557 897450 1568177890 0 1568177890 0 "interfaces//VX_mem_req_inter.v" +S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v" +S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v" +S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v" +T 1312387 897481 1568178034 0 1568178034 0 "obj_dir/VVortex.cpp" +T 23516 897479 1568178032 0 1568178032 0 "obj_dir/VVortex.h" +T 1791 897581 1568178034 0 1568178034 0 "obj_dir/VVortex.mk" +T 914 897569 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.cpp" +T 1029 897568 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.h" +T 1210 897565 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp" +T 1135 897564 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.h" +T 988 897563 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp" +T 1045 897562 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.h" +T 1059 897567 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp" +T 1142 897566 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h" +T 884 897577 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp" +T 1008 897576 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h" +T 865 897573 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp" +T 987 897572 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.h" +T 885 897575 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.cpp" +T 1005 897574 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.h" +T 902 897571 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp" +T 1017 897570 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.h" +T 825 897579 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.cpp" +T 954 897578 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.h" +T 3499 897478 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.cpp" +T 1855 897477 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.h" +T 2113 897582 1568178034 0 1568178034 0 "obj_dir/VVortex__ver.d" +T 0 0 1568178034 0 1568178034 0 "obj_dir/VVortex__verFiles.dat" +T 1530 897580 1568178034 0 1568178034 0 "obj_dir/VVortex_classes.mk" +S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v" +S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v" +S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v" +S 688 897457 1568177900 0 1568177900 0 "pipe_regs//VX_m_w_reg.v" diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o index ad0450d3..4aef2646 100644 Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ diff --git a/rtl/quartus/._Makefile b/rtl/quartus/._Makefile deleted file mode 100644 index 02b577d6..00000000 Binary files a/rtl/quartus/._Makefile and /dev/null differ diff --git a/rtl/quartus/._project.tcl b/rtl/quartus/._project.tcl deleted file mode 100644 index 02b577d6..00000000 Binary files a/rtl/quartus/._project.tcl and /dev/null differ diff --git a/rtl/quartus/VX_gpr_syn.qpf b/rtl/quartus/VX_gpr_syn.qpf new file mode 100644 index 00000000..8938d2a9 --- /dev/null +++ b/rtl/quartus/VX_gpr_syn.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition +# Date created = 00:18:19 September 11, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "00:18:19 September 11, 2019" + +# Revisions + +PROJECT_REVISION = "VX_gpr_syn" diff --git a/rtl/quartus/VX_gpr_syn.qsf b/rtl/quartus/VX_gpr_syn.qsf new file mode 100644 index 00000000..26b4649b --- /dev/null +++ b/rtl/quartus/VX_gpr_syn.qsf @@ -0,0 +1,63 @@ +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition" +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name DEVICE 10AX115N4F45I3SG +set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn +set_global_assignment -name SEARCH_PATH ../ +set_global_assignment -name VERILOG_FILE ../VX_define.v +set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v +set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v +set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v +set_global_assignment -name VERILOG_FILE ../VX_alu.v +set_global_assignment -name VERILOG_FILE ../VX_back_end.v +set_global_assignment -name VERILOG_FILE ../VX_context.v +set_global_assignment -name VERILOG_FILE ../VX_context_slave.v +set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v +set_global_assignment -name VERILOG_FILE ../VX_decode.v +set_global_assignment -name VERILOG_FILE ../VX_execute.v +set_global_assignment -name VERILOG_FILE ../VX_fetch.v +set_global_assignment -name VERILOG_FILE ../VX_forwarding.v +set_global_assignment -name VERILOG_FILE ../VX_front_end.v +set_global_assignment -name VERILOG_FILE ../VX_generic_register.v +set_global_assignment -name VERILOG_FILE ../VX_gpr.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v +set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v +set_global_assignment -name VERILOG_FILE ../VX_memory.v +set_global_assignment -name VERILOG_FILE ../VX_register_file.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v +set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v +set_global_assignment -name VERILOG_FILE ../VX_warp.v +set_global_assignment -name VERILOG_FILE ../VX_writeback.v +set_global_assignment -name VERILOG_FILE ../Vortex.v +set_global_assignment -name SDC_FILE vortex.sdc +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL diff --git a/rtl/quartus/asm.chg b/rtl/quartus/asm.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/rtl/quartus/asm.chg @@ -0,0 +1 @@ +done diff --git a/rtl/quartus/fit.chg b/rtl/quartus/fit.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/rtl/quartus/fit.chg @@ -0,0 +1 @@ +done diff --git a/rtl/quartus/map.chg b/rtl/quartus/map.chg new file mode 100644 index 00000000..d155914e --- /dev/null +++ b/rtl/quartus/map.chg @@ -0,0 +1 @@ +Wed Sep 11 00:18:22 2019 diff --git a/rtl/quartus/project.tcl b/rtl/quartus/project.tcl index 6639dd13..49e1d8ac 100644 --- a/rtl/quartus/project.tcl +++ b/rtl/quartus/project.tcl @@ -21,6 +21,8 @@ set_global_assignment -name SEARCH_PATH ../ set_global_assignment -name VERILOG_FILE ../VX_define.v +set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v + set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v diff --git a/rtl/quartus/smart.log b/rtl/quartus/smart.log new file mode 100644 index 00000000..540778b5 --- /dev/null +++ b/rtl/quartus/smart.log @@ -0,0 +1,27 @@ +Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support. +Info: ******************************************************************* +Info: Running Quartus Prime Shell + Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition + Info: Copyright (C) 2018 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and its AMPP partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details. + Info: Processing started: Wed Sep 11 00:18:22 2019 +Info: Command: quartus_sh --determine_smart_action VX_gpr_syn +Info: Quartus(args): VX_gpr_syn +Info: SMART_ACTION = SOURCE +Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 687 megabytes + Info: Processing ended: Wed Sep 11 00:18:22 2019 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 diff --git a/rtl/quartus/sta.chg b/rtl/quartus/sta.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/rtl/quartus/sta.chg @@ -0,0 +1 @@ +done diff --git a/rtl/quartus/syn.chg b/rtl/quartus/syn.chg new file mode 100644 index 00000000..19f86f49 --- /dev/null +++ b/rtl/quartus/syn.chg @@ -0,0 +1 @@ +done diff --git a/rtl/ram.h b/rtl/ram.h index 1614fdc2..d120178d 100644 --- a/rtl/ram.h +++ b/rtl/ram.h @@ -1,4 +1,3 @@ - #ifndef __RAM__ #define __RAM__ diff --git a/rtl/results.txt b/rtl/results.txt index bbf9acd3..bc1ea005 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -3,5 +3,5 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.00015 -# time to simulate: 2.22726e-314 milliseconds +# time to simulate: 2.18298e-314 milliseconds # GRADE: Failed on test: 4294967295 diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp index b2fbe505..5ec1d250 100644 --- a/rtl/test_bench.cpp +++ b/rtl/test_bench.cpp @@ -1,5 +1,3 @@ - - #include "test_bench.h" #define NUM_TESTS 46 @@ -88,6 +86,3 @@ int main(int argc, char **argv) return 0; } - - - diff --git a/rtl/test_bench.h b/rtl/test_bench.h index 3491d7be..10a5214d 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -1,5 +1,3 @@ - - // C++ libraries #include #include @@ -397,14 +395,4 @@ bool Vortex::simulate(std::string file_to_simulate) return (status == 1); -} - - - - - - - - - - +} \ No newline at end of file diff --git a/rtl/worst_case_paths.rpt b/rtl/worst_case_paths.rpt deleted file mode 100644 index 98f8d7ef..00000000 --- a/rtl/worst_case_paths.rpt +++ /dev/null @@ -1,215904 +0,0 @@ ----------------- -; Command Info ; ----------------- -Report Timing: Found 2000 setup paths (2000 violated). Worst case slack is -0.962 - -Tcl Command: - report_timing -setup -multi_corner -file worst_case_paths.rpt -panel_name {Report Timing} -npaths 2000 -detail full_path - -Options: - -setup - -npaths 2000 - -detail full_path - -panel_name {Report Timing} - -file {worst_case_paths.rpt} - -multi_corner - -Snapshot: - final - -Delay Model: - Fast 900mV 100C Model - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Summary of Paths ; -+--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ -; -0.962 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.489 ; -; -0.960 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.488 ; -; -0.946 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.475 ; -; -0.932 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.482 ; -; -0.932 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.483 ; -; -0.931 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.480 ; -; -0.924 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.512 ; -; -0.913 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.514 ; -; -0.910 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.484 ; -; -0.909 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.459 ; -; -0.898 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.510 ; -; -0.898 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.502 ; -; -0.895 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.367 ; -; -0.893 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.488 ; -; -0.887 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.476 ; -; -0.887 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.476 ; -; -0.886 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.483 ; -; -0.883 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.480 ; -; -0.878 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.452 ; -; -0.875 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.425 ; -; -0.875 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.426 ; -; -0.874 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.423 ; -; -0.870 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.444 ; -; -0.869 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.445 ; -; -0.869 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.444 ; -; -0.867 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.455 ; -; -0.866 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.478 ; -; -0.866 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.455 ; -; -0.865 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.455 ; -; -0.861 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.456 ; -; -0.858 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.470 ; -; -0.855 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.444 ; -; -0.855 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.444 ; -; -0.855 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.444 ; -; -0.854 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.457 ; -; -0.854 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.443 ; -; -0.853 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.448 ; -; -0.852 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.402 ; -; -0.852 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.453 ; -; -0.849 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.399 ; -; -0.849 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.400 ; -; -0.848 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.397 ; -; -0.848 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.119 ; 3.361 ; -; -0.847 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.436 ; -; -0.847 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.436 ; -; -0.846 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.420 ; -; -0.844 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.441 ; -; -0.844 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.418 ; -; -0.844 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.438 ; -; -0.843 ; vx_f_d_reg|instruction[22] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.141 ; 3.264 ; -; -0.843 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.451 ; -; -0.842 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.393 ; -; -0.842 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.392 ; -; -0.842 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.439 ; -; -0.842 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.437 ; -; -0.841 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.390 ; -; -0.841 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.429 ; -; -0.841 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.451 ; -; -0.841 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.437 ; -; -0.838 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.310 ; -; -0.837 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.441 ; -; -0.837 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.367 ; -; -0.836 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.433 ; -; -0.836 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.425 ; -; -0.835 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.366 ; -; -0.834 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.422 ; -; -0.834 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.423 ; -; -0.834 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.431 ; -; -0.834 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.446 ; -; -0.833 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.423 ; -; -0.833 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.407 ; -; -0.833 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.390 ; -; -0.833 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.390 ; -; -0.832 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.444 ; -; -0.831 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.387 ; -; -0.830 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.094 ; 2.410 ; -; -0.829 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.424 ; -; -0.828 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; -; -0.827 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.422 ; -; -0.827 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; -; -0.826 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.376 ; -; -0.826 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.415 ; -; -0.826 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.427 ; -; -0.826 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.379 ; -; -0.825 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.415 ; -; -0.825 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.400 ; -; -0.824 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.425 ; -; -0.824 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.400 ; -; -0.824 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.426 ; -; -0.823 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.412 ; -; -0.823 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.412 ; -; -0.823 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.419 ; -; -0.822 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.411 ; -; -0.822 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.379 ; -; -0.821 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.410 ; -; -0.821 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.410 ; -; -0.821 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.433 ; -; -0.821 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.373 ; -; -0.821 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.353 ; -; -0.820 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.371 ; -; -0.820 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.370 ; -; -0.820 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.394 ; -; -0.819 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.369 ; -; -0.819 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.368 ; -; -0.819 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.375 ; -; -0.818 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.426 ; -; -0.817 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.392 ; -; -0.816 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.392 ; -; -0.816 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.411 ; -; -0.815 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.389 ; -; -0.813 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.424 ; -; -0.812 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.400 ; -; -0.812 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.406 ; -; -0.812 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.409 ; -; -0.812 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.284 ; -; -0.812 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.398 ; -; -0.812 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.424 ; -; -0.810 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.405 ; -; -0.810 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.407 ; -; -0.810 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.407 ; -; -0.810 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.399 ; -; -0.810 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.399 ; -; -0.809 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.413 ; -; -0.809 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.405 ; -; -0.809 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.383 ; -; -0.808 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.405 ; -; -0.808 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.420 ; -; -0.806 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.407 ; -; -0.805 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.277 ; -; -0.804 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.398 ; -; -0.804 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.393 ; -; -0.803 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.406 ; -; -0.803 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.398 ; -; -0.803 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.415 ; -; -0.803 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.389 ; -; -0.803 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.393 ; -; -0.803 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.393 ; -; -0.802 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.397 ; -; -0.802 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.391 ; -; -0.802 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.418 ; -; -0.801 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.397 ; -; -0.801 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.391 ; -; -0.801 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.402 ; -; -0.801 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.351 ; -; -0.801 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.352 ; -; -0.800 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.389 ; -; -0.800 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.398 ; -; -0.800 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.356 ; -; -0.800 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.357 ; -; -0.800 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.349 ; -; -0.799 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.389 ; -; -0.799 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.396 ; -; -0.799 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.401 ; -; -0.799 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; -; -0.799 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.354 ; -; -0.799 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.355 ; -; -0.799 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; -; -0.799 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; -; -0.798 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.387 ; -; -0.798 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.393 ; -; -0.798 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.355 ; -; -0.798 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.401 ; -; -0.797 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.386 ; -; -0.797 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.347 ; -; -0.797 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.394 ; -; -0.797 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.386 ; -; -0.797 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.386 ; -; -0.797 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.409 ; -; -0.797 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.384 ; -; -0.797 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.353 ; -; -0.796 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.397 ; -; -0.796 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.385 ; -; -0.796 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; -; -0.796 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.351 ; -; -0.795 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.398 ; -; -0.795 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; -; -0.795 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.380 ; -; -0.794 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.395 ; -; -0.794 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.397 ; -; -0.793 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.368 ; -; -0.793 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.381 ; -; -0.793 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.349 ; -; -0.793 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.350 ; -; -0.792 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.394 ; -; -0.792 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.368 ; -; -0.792 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.381 ; -; -0.792 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.381 ; -; -0.792 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.387 ; -; -0.792 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.386 ; -; -0.792 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.347 ; -; -0.791 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.395 ; -; -0.791 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.387 ; -; -0.791 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.366 ; -; -0.790 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.366 ; -; -0.789 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.393 ; -; -0.789 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.340 ; -; -0.789 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.339 ; -; -0.789 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.378 ; -; -0.788 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.337 ; -; -0.788 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.378 ; -; -0.788 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.374 ; -; -0.787 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.375 ; -; -0.786 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.394 ; -; -0.786 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.387 ; -; -0.786 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.383 ; -; -0.786 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.375 ; -; -0.786 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.375 ; -; -0.785 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.379 ; -; -0.784 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.386 ; -; -0.784 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.381 ; -; -0.783 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.379 ; -; -0.783 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.255 ; -; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; -; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; -; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; -; -0.782 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.390 ; -; -0.782 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.090 ; 2.366 ; -; -0.781 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.369 ; -; -0.781 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.378 ; -; -0.781 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.383 ; -; -0.781 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.251 ; -; -0.781 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.251 ; -; -0.781 ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.416 ; -; -0.780 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.390 ; -; -0.780 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.374 ; -; -0.780 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.355 ; -; -0.780 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; -; -0.780 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_one|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.342 ; -; -0.780 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_two|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.341 ; -; -0.780 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; -; -0.779 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.367 ; -; -0.779 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.355 ; -; -0.779 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.376 ; -; -0.778 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.363 ; -; -0.778 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.386 ; -; -0.778 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.373 ; -; -0.778 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.372 ; -; -0.778 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.328 ; -; -0.777 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.373 ; -; -0.777 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.351 ; -; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; -; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; -; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; -; -0.777 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.333 ; -; -0.776 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.371 ; -; -0.776 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.365 ; -; -0.776 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; -; -0.776 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.332 ; -; -0.776 ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.408 ; -; -0.775 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.371 ; -; -0.775 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.365 ; -; -0.775 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.372 ; -; -0.775 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.370 ; -; -0.775 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.090 ; 2.359 ; -; -0.773 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.370 ; -; -0.772 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.361 ; -; -0.772 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.329 ; -; -0.772 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.329 ; -; -0.772 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.361 ; -; -0.771 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.360 ; -; -0.771 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.360 ; -; -0.770 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.371 ; -; -0.770 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.386 ; -; -0.770 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.355 ; -; -0.770 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.326 ; -; -0.770 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.359 ; -; -0.770 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.373 ; -; -0.770 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.360 ; -; -0.770 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.326 ; -; -0.770 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.397 ; -; -0.769 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.370 ; -; -0.769 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.355 ; -; -0.769 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.370 ; -; -0.768 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.366 ; -; -0.768 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.371 ; -; -0.767 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.369 ; -; -0.767 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.361 ; -; -0.767 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.342 ; -; -0.767 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.184 ; -; -0.767 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.371 ; -; -0.766 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.316 ; -; -0.766 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.369 ; -; -0.766 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.342 ; -; -0.766 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.184 ; -; -0.765 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.354 ; -; -0.765 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.318 ; -; -0.765 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.360 ; -; -0.765 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; -; -0.765 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.377 ; -; -0.765 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.320 ; -; -0.765 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.389 ; -; -0.764 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.353 ; -; -0.764 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.360 ; -; -0.764 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; -; -0.764 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.349 ; -; -0.764 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.372 ; -; -0.763 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.366 ; -; -0.763 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.348 ; -; -0.763 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.277 ; -; -0.763 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; -; -0.762 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.378 ; -; -0.762 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.363 ; -; -0.762 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; -; -0.762 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.359 ; -; -0.761 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.362 ; -; -0.761 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.347 ; -; -0.761 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; -; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.362 ; -; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.341 ; -; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; -; -0.761 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.317 ; -; -0.760 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.358 ; -; -0.760 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.312 ; -; -0.760 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.362 ; -; -0.760 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.361 ; -; -0.760 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.355 ; -; -0.760 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.317 ; -; -0.759 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.346 ; -; -0.759 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.361 ; -; -0.759 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.355 ; -; -0.759 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.348 ; -; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.355 ; -; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.374 ; -; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.357 ; -; -0.758 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.308 ; -; -0.758 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.309 ; -; -0.758 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.361 ; -; -0.758 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.314 ; -; -0.758 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.360 ; -; -0.758 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.758 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.758 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.350 ; -; -0.758 ; vx_f_d_reg|instruction[22] ; vx_csr_handler|decode_csr_address[4] ; clk ; clk ; 2.500 ; -0.141 ; 3.264 ; -; -0.757 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.306 ; -; -0.757 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.308 ; -; -0.757 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.307 ; -; -0.757 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.353 ; -; -0.757 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.360 ; -; -0.757 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.757 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.756 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.305 ; -; -0.756 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.342 ; -; -0.756 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.331 ; -; -0.756 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.339 ; -; -0.756 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.364 ; -; -0.756 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.309 ; -; -0.755 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.359 ; -; -0.755 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.358 ; -; -0.755 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.340 ; -; -0.755 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.343 ; -; -0.755 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.331 ; -; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; -; -0.754 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.362 ; -; -0.754 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.362 ; -; -0.754 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.348 ; -; -0.754 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.343 ; -; -0.754 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.343 ; -; -0.754 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.355 ; -; -0.754 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.355 ; -; -0.753 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.341 ; -; -0.753 ; vx_f_d_reg|instruction[23] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.141 ; 3.174 ; -; -0.753 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.360 ; -; -0.753 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.367 ; -; -0.753 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.307 ; -; -0.752 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.363 ; -; -0.752 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.362 ; -; -0.752 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.360 ; -; -0.752 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.347 ; -; -0.752 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.224 ; -; -0.752 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.359 ; -; -0.752 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.355 ; -; -0.751 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.363 ; -; -0.751 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.338 ; -; -0.751 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.347 ; -; -0.751 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.079 ; 3.308 ; -; -0.750 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.338 ; -; -0.750 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.348 ; -; -0.749 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.337 ; -; -0.749 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.351 ; -; -0.749 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.350 ; -; -0.749 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.343 ; -; -0.748 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.334 ; -; -0.748 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.352 ; -; -0.748 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.098 ; 2.320 ; -; -0.748 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.331 ; -; -0.747 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.349 ; -; -0.747 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.342 ; -; -0.747 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.357 ; -; -0.746 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.336 ; -; -0.746 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.336 ; -; -0.746 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.331 ; -; -0.746 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.342 ; -; -0.746 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.335 ; -; -0.746 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.342 ; -; -0.746 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.352 ; -; -0.745 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.295 ; -; -0.744 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.295 ; -; -0.744 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.294 ; -; -0.744 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.329 ; -; -0.744 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.301 ; -; -0.744 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.301 ; -; -0.744 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.347 ; -; -0.744 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.352 ; -; -0.743 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.332 ; -; -0.743 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.292 ; -; -0.743 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.338 ; -; -0.743 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.337 ; -; -0.743 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.340 ; -; -0.742 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.331 ; -; -0.742 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.330 ; -; -0.742 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.298 ; -; -0.742 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.209 ; -; -0.742 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.209 ; -; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.338 ; -; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.325 ; -; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.349 ; -; -0.741 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.343 ; -; -0.741 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.349 ; -; -0.741 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.336 ; -; -0.741 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.344 ; -; -0.741 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.338 ; -; -0.741 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.330 ; -; -0.740 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.336 ; -; -0.740 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.350 ; -; -0.740 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.338 ; -; -0.740 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.347 ; -; -0.740 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.306 ; -; -0.740 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.306 ; -; -0.739 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.156 ; -; -0.739 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.320 ; -; -0.739 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.246 ; -; -0.739 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.338 ; -; -0.738 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.365 ; -; -0.738 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; -; -0.738 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.345 ; -; -0.738 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.294 ; -; -0.738 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.354 ; -; -0.738 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.156 ; -; -0.738 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.338 ; -; -0.738 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.343 ; -; -0.738 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.293 ; -; -0.737 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.294 ; -; -0.737 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.338 ; -; -0.737 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.323 ; -; -0.737 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.290 ; -; -0.736 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.344 ; -; -0.736 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.324 ; -; -0.736 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.292 ; -; -0.736 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.334 ; -; -0.736 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.352 ; -; -0.736 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.337 ; -; -0.736 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.346 ; -; -0.735 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.285 ; -; -0.735 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; -; -0.735 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.330 ; -; -0.735 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.290 ; -; -0.735 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.337 ; -; -0.735 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.336 ; -; -0.735 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.321 ; -; -0.735 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.324 ; -; -0.734 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.344 ; -; -0.734 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.284 ; -; -0.734 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; -; -0.734 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.341 ; -; -0.734 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.337 ; -; -0.734 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.332 ; -; -0.734 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.336 ; -; -0.734 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.119 ; 3.247 ; -; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.332 ; -; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.335 ; -; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.351 ; -; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; -; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.351 ; -; -0.733 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.357 ; -; -0.733 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; -; -0.733 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.318 ; -; -0.733 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.329 ; -; -0.733 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.336 ; -; -0.733 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; -; -0.733 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.325 ; -; -0.733 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.336 ; -; -0.732 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.317 ; -; -0.732 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; -; -0.732 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.284 ; -; -0.732 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; -; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.325 ; -; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.316 ; -; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.330 ; -; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.338 ; -; -0.731 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.305 ; -; -0.731 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.316 ; -; -0.731 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.334 ; -; -0.731 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.332 ; -; -0.731 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.348 ; -; -0.730 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.331 ; -; -0.730 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.286 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.330 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.326 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.332 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.343 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.326 ; -; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.342 ; -; -0.729 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.286 ; -; -0.729 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.285 ; -; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.309 ; -; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; -; -0.729 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.314 ; -; -0.729 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.332 ; -; -0.729 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.317 ; -; -0.729 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.331 ; -; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.330 ; -; -0.729 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.330 ; -; -0.729 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; -; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; -; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.285 ; -; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.284 ; -; -0.728 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.336 ; -; -0.728 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.324 ; -; -0.728 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.280 ; -; -0.728 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.347 ; -; -0.728 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.348 ; -; -0.727 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.342 ; -; -0.727 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.323 ; -; -0.727 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.282 ; -; -0.727 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.314 ; -; -0.727 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.324 ; -; -0.727 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.327 ; -; -0.726 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.334 ; -; -0.726 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.318 ; -; -0.726 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; -; -0.726 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; -; -0.726 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.333 ; -; -0.726 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.334 ; -; -0.725 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.312 ; -; -0.725 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.341 ; -; -0.725 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.326 ; -; -0.725 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.314 ; -; -0.725 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.314 ; -; -0.724 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.335 ; -; -0.724 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.334 ; -; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.307 ; -; -0.724 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.309 ; -; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.328 ; -; -0.724 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.310 ; -; -0.724 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.325 ; -; -0.724 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.310 ; -; -0.724 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.312 ; -; -0.724 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.280 ; -; -0.724 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.299 ; -; -0.724 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.194 ; -; -0.724 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.194 ; -; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.332 ; -; -0.724 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.313 ; -; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; -; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.340 ; -; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.315 ; -; -0.723 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.335 ; -; -0.723 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.333 ; -; -0.723 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.297 ; -; -0.723 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.318 ; -; -0.723 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.321 ; -; -0.723 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.331 ; -; -0.723 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.274 ; -; -0.723 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.325 ; -; -0.723 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.299 ; -; -0.723 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.312 ; -; -0.723 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.318 ; -; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.308 ; -; -0.723 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[2] ; clk ; clk ; 2.500 ; -0.077 ; 3.169 ; -; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.324 ; -; -0.723 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[5] ; clk ; clk ; 2.500 ; -0.077 ; 3.169 ; -; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.315 ; -; -0.722 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.323 ; -; -0.722 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.320 ; -; -0.722 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.323 ; -; -0.722 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.308 ; -; -0.722 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; -; -0.722 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.318 ; -; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; -; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; -; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; -; -0.722 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.317 ; -; -0.722 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.337 ; -; -0.721 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.315 ; -; -0.721 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.271 ; -; -0.721 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.335 ; -; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.314 ; -; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.301 ; -; -0.721 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; -; -0.721 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.138 ; -; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.322 ; -; -0.721 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.300 ; -; -0.721 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.287 ; -; -0.720 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.310 ; -; -0.720 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.310 ; -; -0.720 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.271 ; -; -0.720 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.270 ; -; -0.720 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.323 ; -; -0.720 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.314 ; -; -0.720 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.305 ; -; -0.720 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.138 ; -; -0.720 ; vx_f_d_reg|instruction[5] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.192 ; -; -0.720 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.286 ; -; -0.720 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[4] ; clk ; clk ; 2.500 ; -0.122 ; 3.234 ; -; -0.719 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.268 ; -; -0.719 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.329 ; -; -0.719 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.334 ; -; -0.719 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.315 ; -; -0.719 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.272 ; -; -0.719 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; -; -0.719 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; -; -0.719 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.320 ; -; -0.719 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.268 ; -; -0.719 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[29] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.718 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.316 ; -; -0.718 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.310 ; -; -0.718 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.303 ; -; -0.718 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.321 ; -; -0.718 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.306 ; -; -0.718 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[27] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.718 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.272 ; -; -0.717 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.319 ; -; -0.717 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.325 ; -; -0.717 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[26] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.299 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.320 ; -; -0.716 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.273 ; -; -0.716 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.273 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; -; -0.716 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.183 ; -; -0.716 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.183 ; -; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.324 ; -; -0.716 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.311 ; -; -0.716 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.295 ; -; -0.715 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.271 ; -; -0.715 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.317 ; -; -0.715 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.300 ; -; -0.715 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; -; -0.715 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.310 ; -; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.321 ; -; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.290 ; -; -0.715 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[2] ; clk ; clk ; 2.500 ; -0.122 ; 3.229 ; -; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.312 ; -; -0.714 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.320 ; -; -0.714 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.315 ; -; -0.714 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.312 ; -; -0.714 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.301 ; -; -0.714 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.266 ; -; -0.714 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.270 ; -; -0.714 ; vx_csr_handler|decode_csr_address[1] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.338 ; -; -0.714 ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.338 ; -; -0.714 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.303 ; -; -0.714 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.320 ; -; -0.713 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.303 ; -; -0.713 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.303 ; -; -0.713 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.327 ; -; -0.713 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.312 ; -; -0.713 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[30] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.301 ; -; -0.712 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.300 ; -; -0.712 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.315 ; -; -0.712 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.319 ; -; -0.712 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.269 ; -; -0.712 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.268 ; -; -0.712 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.328 ; -; -0.712 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.268 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[22] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[23] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[24] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[28] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.295 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[31] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.712 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.309 ; -; -0.711 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.312 ; -; -0.711 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.300 ; -; -0.711 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.308 ; -; -0.711 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.306 ; -; -0.711 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.297 ; -; -0.711 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; -; -0.711 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.312 ; -; -0.711 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.297 ; -; -0.711 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.305 ; -; -0.711 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.128 ; -; -0.711 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.321 ; -; -0.711 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.306 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.295 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[25] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.314 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.313 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; clk ; clk ; 2.500 ; -0.082 ; 3.249 ; -; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.299 ; -; -0.710 ; vx_f_d_reg|instruction[5] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.311 ; -; -0.710 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; -; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.293 ; -; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.317 ; -; -0.710 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.308 ; -; -0.710 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; -; -0.710 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.308 ; -; -0.710 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.128 ; -; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.306 ; -; -0.709 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.304 ; -; -0.709 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; -; -0.709 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.311 ; -; -0.709 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.294 ; -; -0.709 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.304 ; -; -0.709 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.176 ; -; -0.709 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.176 ; -; -0.709 ; vx_d_e_reg|rd[4] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.181 ; -; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.302 ; -; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.302 ; -; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.310 ; -; -0.708 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.306 ; -; -0.708 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.264 ; -; -0.708 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.311 ; -; -0.708 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.304 ; -; -0.708 ; vx_f_d_reg|instruction[23] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.020 ; 3.186 ; -; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; -; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.321 ; -; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.298 ; -; -0.708 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[14] ; clk ; clk ; 2.500 ; -0.078 ; 3.261 ; -; -0.707 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; -; -0.707 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; -; -0.707 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.323 ; -; -0.707 ; vx_f_d_reg|instruction[1] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.179 ; -; -0.707 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.306 ; -; -0.707 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.303 ; -; -0.706 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; -; -0.706 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.318 ; -; -0.706 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.317 ; -; -0.706 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; -; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.311 ; -; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.314 ; -; -0.706 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.312 ; -; -0.706 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.220 ; -; -0.706 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.333 ; -; -0.706 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.307 ; -; -0.706 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.292 ; -; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; -; -0.706 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.323 ; -; -0.706 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_one|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.093 ; 2.283 ; -; -0.706 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_two|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.093 ; 2.282 ; -; -0.705 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.309 ; -; -0.705 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.317 ; -; -0.705 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.261 ; -; -0.705 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; -; -0.705 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.261 ; -; -0.705 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.290 ; -; -0.705 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.308 ; -; -0.705 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.303 ; -; -0.705 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.295 ; -; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[5] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; -; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[7] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; -; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[11] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; -; -0.705 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_one|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.227 ; -; -0.705 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.307 ; -; -0.704 ; vx_f_d_reg|instruction[5] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.308 ; -; -0.704 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.259 ; -; -0.704 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.306 ; -; -0.704 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.259 ; -; -0.704 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; -; -0.704 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.293 ; -; -0.704 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; -; -0.703 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.311 ; -; -0.703 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.300 ; -; -0.703 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; -; -0.703 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.292 ; -; -0.703 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[6] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; -; -0.703 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.305 ; -; -0.703 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.309 ; -; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.309 ; -; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; -; -0.702 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.258 ; -; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.300 ; -; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.319 ; -; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; -; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.319 ; -; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.298 ; -; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.259 ; -; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.258 ; -; -0.702 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; -; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[5] ; clk ; clk ; 2.500 ; -0.116 ; 3.220 ; -; -0.702 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.278 ; -; -0.701 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.304 ; -; -0.701 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.284 ; -; -0.701 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.325 ; -; -0.701 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.288 ; -; -0.701 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.317 ; -; -0.701 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.304 ; -; -0.701 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.256 ; -; -0.701 ; vx_f_d_reg|instruction[22] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.020 ; 3.179 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.305 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.300 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.290 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.296 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[26] ; clk ; clk ; 2.500 ; -0.082 ; 3.249 ; -; -0.701 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_two|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.262 ; -; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.297 ; -; -0.700 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.254 ; -; -0.700 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; -; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.284 ; -; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.293 ; -; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.307 ; -; -0.700 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.298 ; -; -0.700 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; -; -0.700 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; -; -0.700 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.303 ; -; -0.700 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.301 ; -; -0.700 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.286 ; -; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; -; -0.700 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.307 ; -; -0.699 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.273 ; -; -0.699 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.297 ; -; -0.699 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.316 ; -; -0.699 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.298 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.298 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.294 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.311 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.310 ; -; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.300 ; -; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.303 ; -; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.306 ; -; -0.698 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.283 ; -; -0.698 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.299 ; -; -0.698 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.293 ; -; -0.698 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.284 ; -; -0.698 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.300 ; -; -0.698 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.168 ; -; -0.698 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.168 ; -; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.298 ; -; -0.698 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.287 ; -; -0.698 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.300 ; -; -0.697 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.254 ; -; -0.697 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.253 ; -; -0.697 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.246 ; -; -0.697 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; -; -0.697 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.247 ; -; -0.697 ; vx_f_d_reg|instruction[1] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; -; -0.697 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.697 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.697 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; -; -0.697 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.307 ; -; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.290 ; -; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.277 ; -; -0.697 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.271 ; -; -0.697 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.291 ; -; -0.697 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.300 ; -; -0.697 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; -; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; -; -0.697 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; -; -0.697 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_two|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.219 ; -; -0.696 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.251 ; -; -0.696 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.696 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.696 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.315 ; -; -0.696 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.316 ; -; -0.696 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.297 ; -; -0.696 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.283 ; -; -0.696 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; -; -0.696 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[13] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; -; -0.696 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.298 ; -; -0.695 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.302 ; -; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.295 ; -; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.293 ; -; -0.695 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.248 ; -; -0.695 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.310 ; -; -0.695 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.291 ; -; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.288 ; -; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.275 ; -; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.292 ; -; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.296 ; -; -0.695 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[19] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; -; -0.694 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.302 ; -; -0.694 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.286 ; -; -0.694 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.279 ; -; -0.694 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.297 ; -; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; -; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; -; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.311 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.295 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.311 ; -; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.292 ; -; -0.693 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.282 ; -; -0.693 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.282 ; -; -0.693 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.296 ; -; -0.693 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.276 ; -; -0.693 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.300 ; -; -0.693 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.308 ; -; -0.693 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.289 ; -; -0.693 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.279 ; -; -0.693 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.294 ; -; -0.693 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.248 ; -; -0.693 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.278 ; -; -0.693 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_three|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.214 ; -; -0.692 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; -; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.283 ; -; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.308 ; -; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.288 ; -; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.276 ; -; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.285 ; -; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.299 ; -; -0.692 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.246 ; -; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.275 ; -; -0.692 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.284 ; -; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.296 ; -; -0.692 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; -; -0.692 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.249 ; -; -0.692 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; -; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.298 ; -; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.300 ; -; -0.692 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.277 ; -; -0.692 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.284 ; -; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.281 ; -; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.281 ; -; -0.691 ; vx_f_d_reg|instruction[1] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.295 ; -; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; -; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.283 ; -; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.276 ; -; -0.691 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.293 ; -; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; -; -0.691 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; -; -0.691 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.293 ; -; -0.691 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; -; -0.691 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; -; -0.691 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.161 ; -; -0.691 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.161 ; -; -0.691 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.308 ; -; -0.691 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[21] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; -; -0.691 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[3] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; -; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; -; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.305 ; -; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; -; -0.691 ; vx_d_e_reg|a_reg_data[0] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.245 ; -; -0.690 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.305 ; -; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.302 ; -; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.303 ; -; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.292 ; -; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.290 ; -; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.286 ; -; -0.690 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.291 ; -; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.273 ; -; -0.690 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.288 ; -; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.294 ; -; -0.690 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; -; -0.690 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; -; -0.690 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.277 ; -; -0.690 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.286 ; -; -0.690 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.247 ; -; -0.690 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.247 ; -; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; -; -0.690 ; vx_csr_handler|decode_csr_address[1] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; 0.005 ; 3.329 ; -; -0.690 ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; 0.005 ; 3.329 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.285 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.274 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; -; -0.690 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.246 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[31] ; clk ; clk ; 2.500 ; -0.023 ; 3.165 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[28] ; clk ; clk ; 2.500 ; -0.023 ; 3.165 ; -; -0.690 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.079 ; 3.247 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.274 ; -; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.310 ; -; -0.689 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; -; -0.689 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; -; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.268 ; -; -0.689 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.290 ; -; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.291 ; -; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.270 ; -; -0.689 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.303 ; -; -0.689 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.244 ; -; -0.689 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.295 ; -; -0.689 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[15] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; -; -0.689 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; -; -0.689 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.246 ; -; -0.689 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.283 ; -; -0.688 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.239 ; -; -0.688 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.238 ; -; -0.688 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.286 ; -; -0.688 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; -; -0.688 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.307 ; -; -0.688 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.291 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.289 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.243 ; -; -0.688 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.244 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; -; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; -; -0.688 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.312 ; -; -0.687 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.236 ; -; -0.687 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.288 ; -; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.287 ; -; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.285 ; -; -0.687 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.301 ; -; -0.687 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.272 ; -; -0.687 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.273 ; -; -0.687 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; -; -0.687 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.154 ; -; -0.687 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.154 ; -; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.284 ; -; -0.687 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[18] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; -; -0.687 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.278 ; -; -0.687 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.278 ; -; -0.687 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[2] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; -; -0.687 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.239 ; -; -0.686 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; -; -0.686 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.284 ; -; -0.686 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.289 ; -; -0.686 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.260 ; -; -0.686 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.288 ; -; -0.686 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.274 ; -; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.242 ; -; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.276 ; -; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.281 ; -; -0.686 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.244 ; -; -0.685 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.274 ; -; -0.685 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.274 ; -; -0.685 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.286 ; -; -0.685 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.280 ; -; -0.685 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.293 ; -; -0.685 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.102 ; -; -0.685 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.269 ; -; -0.685 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[4] ; clk ; clk ; 2.500 ; -0.080 ; 3.240 ; -; -0.685 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; -; -0.684 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.263 ; -; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.275 ; -; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.300 ; -; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.280 ; -; -0.684 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.234 ; -; -0.684 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.282 ; -; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.277 ; -; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.264 ; -; -0.684 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.278 ; -; -0.684 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.102 ; -; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; -; -0.684 ; vx_f_d_reg|instruction[24] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.126 ; 3.120 ; -; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.275 ; -; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.286 ; -; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; -; -0.683 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.234 ; -; -0.683 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.233 ; -; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.289 ; -; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.258 ; -; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; -; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.275 ; -; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.268 ; -; -0.683 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.236 ; -; -0.683 ; vx_f_d_reg|instruction[6] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.155 ; -; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.280 ; -; -0.683 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; -; -0.683 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.289 ; -; -0.682 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.231 ; -; -0.682 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; -; -0.682 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; -; -0.682 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.274 ; -; -0.682 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.189 ; -; -0.682 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.288 ; -; -0.682 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; -; -0.682 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.278 ; -; -0.682 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; -; -0.682 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; -; -0.682 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.296 ; -; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; -; -0.682 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.233 ; -; -0.682 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.291 ; -; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.284 ; -; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.285 ; -; -0.681 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.270 ; -; -0.681 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.288 ; -; -0.681 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; -; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.260 ; -; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.283 ; -; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.262 ; -; -0.681 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; -; -0.681 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; -; -0.681 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; -; -0.681 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.280 ; -; -0.681 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.238 ; -; -0.681 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; -; -0.681 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.262 ; -; -0.680 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.269 ; -; -0.680 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.290 ; -; -0.680 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.269 ; -; -0.680 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.268 ; -; -0.680 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; -; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.263 ; -; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.286 ; -; -0.680 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.286 ; -; -0.680 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.194 ; -; -0.680 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.275 ; -; -0.680 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; -; -0.680 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; -; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.277 ; -; -0.680 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.296 ; -; -0.680 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[15] ; clk ; clk ; 2.500 ; -0.080 ; 3.240 ; -; -0.680 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.090 ; -; -0.679 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.268 ; -; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.282 ; -; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.281 ; -; -0.679 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.280 ; -; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.279 ; -; -0.679 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.276 ; -; -0.679 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; -; -0.679 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; -; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.262 ; -; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.283 ; -; -0.679 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.234 ; -; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.287 ; -; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.235 ; -; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; -; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.237 ; -; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.090 ; -; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; -; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.277 ; -; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.285 ; -; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.261 ; -; -0.678 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.288 ; -; -0.678 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.230 ; -; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.274 ; -; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; -; -0.678 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[2] ; clk ; clk ; 2.500 ; -0.084 ; 3.226 ; -; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; -; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; -; -0.678 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; -; -0.677 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.284 ; -; -0.677 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.275 ; -; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.270 ; -; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.270 ; -; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.266 ; -; -0.677 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.278 ; -; -0.677 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.274 ; -; -0.677 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.262 ; -; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.284 ; -; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.256 ; -; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; clk ; clk ; 2.500 ; -0.033 ; 3.278 ; -; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.283 ; -; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.266 ; -; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.289 ; -; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.277 ; -; -0.676 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.255 ; -; -0.676 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.274 ; -; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.283 ; -; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.259 ; -; -0.676 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.290 ; -; -0.676 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.231 ; -; -0.676 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.232 ; -; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; -; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; -; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; -; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; -; -0.675 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.263 ; -; -0.675 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.285 ; -; -0.675 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.283 ; -; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.281 ; -; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.250 ; -; -0.675 ; vx_d_e_reg|b_reg_data[28] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.224 ; -; -0.675 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.278 ; -; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; -; -0.675 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.274 ; -; -0.675 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.295 ; -; -0.675 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.026 ; 3.295 ; -; -0.674 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.230 ; -; -0.674 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; -; -0.674 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; -; -0.674 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; -; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.279 ; -; -0.674 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.272 ; -; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.282 ; -; -0.674 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.259 ; -; -0.674 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.269 ; -; -0.674 ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.309 ; -; -0.674 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.229 ; -; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; -; -0.674 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.264 ; -; -0.674 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.231 ; -; -0.674 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.265 ; -; -0.673 ; vx_f_d_reg|instruction[6] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.274 ; -; -0.673 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; -; -0.673 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.263 ; -; -0.673 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.271 ; -; -0.673 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.187 ; -; -0.673 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.247 ; -; -0.673 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; -; -0.673 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; -; -0.673 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; -; -0.673 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; -; -0.672 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.261 ; -; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.255 ; -; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.278 ; -; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; -; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.277 ; -; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.280 ; -; -0.672 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.273 ; -; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.269 ; -; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; -; -0.672 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.104 ; 3.200 ; -; -0.672 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.262 ; -; -0.672 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.262 ; -; -0.672 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.235 ; -; -0.672 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.295 ; -; -0.672 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.235 ; -; -0.672 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_one|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.233 ; -; -0.672 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.295 ; -; -0.671 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; -; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.273 ; -; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.274 ; -; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.264 ; -; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.251 ; -; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; -; -0.671 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.074 ; 3.267 ; -; -0.671 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.074 ; 3.267 ; -; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.255 ; -; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.273 ; -; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.274 ; -; -0.671 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.190 ; -; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; -; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.273 ; -; -0.670 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.297 ; -; -0.670 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; -; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; -; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; -; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; -; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; -; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; -; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; -; -0.670 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.262 ; -; -0.670 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.232 ; -; -0.670 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; clk ; clk ; 2.500 ; -0.032 ; 3.290 ; -; -0.669 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; -; -0.669 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.669 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; -; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.265 ; -; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; -; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; -; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.262 ; -; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.262 ; -; -0.669 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; -; -0.669 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.275 ; -; -0.669 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.252 ; -; -0.669 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; -; -0.669 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.265 ; -; -0.669 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.254 ; -; -0.669 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.225 ; -; -0.669 ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.301 ; -; -0.669 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.225 ; -; -0.669 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; -; -0.669 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; -; -0.669 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.139 ; -; -0.669 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.139 ; -; -0.669 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.283 ; -; -0.669 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.270 ; -; -0.668 ; vx_d_e_reg|b_reg_data[4] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.221 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.668 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; -; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; -; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; -; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; -; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; -; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.281 ; -; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.269 ; -; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.252 ; -; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.261 ; -; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.275 ; -; -0.668 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.260 ; -; -0.668 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.242 ; -; -0.668 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.269 ; -; -0.668 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.254 ; -; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.269 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; -; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.266 ; -; -0.668 ; vx_f_d_reg|instruction[23] ; vx_csr_handler|decode_csr_address[4] ; clk ; clk ; 2.500 ; -0.141 ; 3.174 ; -; -0.668 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.046 ; 3.268 ; -; -0.668 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.292 ; -; -0.668 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.101 ; 2.237 ; -; -0.667 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.268 ; -; -0.667 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.256 ; -; -0.667 ; vx_f_d_reg|instruction[6] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.271 ; -; -0.667 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; -; -0.667 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; -; -0.667 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.250 ; -; -0.667 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.220 ; -; -0.667 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.268 ; -; -0.667 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.265 ; -; -0.667 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.284 ; -; -0.667 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.275 ; -; -0.667 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.252 ; -; -0.666 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.276 ; -; -0.666 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.273 ; -; -0.666 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.255 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; -; -0.666 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; -; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.255 ; -; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.270 ; -; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.283 ; -; -0.666 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; -; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.278 ; -; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.279 ; -; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; -; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.266 ; -; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.262 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.250 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.259 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.273 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.249 ; -; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.259 ; -; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.246 ; -; -0.666 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.263 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.270 ; -; -0.666 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.268 ; -; -0.666 ; vx_d_e_reg|rd[3] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.138 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; -; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; -; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.274 ; -; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; -; -0.666 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.076 ; -; -0.666 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.280 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.254 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.251 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.268 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[2] ; clk ; clk ; 2.500 ; -0.080 ; 3.221 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; clk ; clk ; 2.500 ; -0.033 ; 3.268 ; -; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; -; -0.665 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.289 ; -; -0.665 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.215 ; -; -0.665 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.665 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; -; -0.665 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.255 ; -; -0.665 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; -; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; -; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.248 ; -; -0.665 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.268 ; -; -0.665 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.665 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.282 ; -; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.261 ; -; -0.665 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.076 ; -; -0.665 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.277 ; -; -0.665 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.275 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; clk ; clk ; 2.500 ; -0.046 ; 3.265 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; clk ; clk ; 2.500 ; -0.029 ; 3.281 ; -; -0.665 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.222 ; -; -0.665 ; vx_d_e_reg|a_reg_data[0] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.220 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; clk ; clk ; 2.500 ; -0.034 ; 3.266 ; -; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.246 ; -; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.220 ; -; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.221 ; -; -0.664 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.278 ; -; -0.664 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.253 ; -; -0.664 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.284 ; -; -0.664 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.283 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.276 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.277 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.264 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.260 ; -; -0.664 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.218 ; -; -0.664 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; -; -0.664 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.262 ; -; -0.664 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.279 ; -; -0.664 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.260 ; -; -0.664 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; -; -0.664 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.280 ; -; -0.664 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.074 ; 3.260 ; -; -0.664 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.074 ; 3.260 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.258 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.252 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[11] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.265 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[7] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.229 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.227 ; -; -0.664 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.220 ; -; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.262 ; -; -0.663 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.218 ; -; -0.663 ; vx_csr_handler|decode_csr_address[6] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.268 ; -; -0.663 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; -; -0.663 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; -; -0.663 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[4] ; clk ; clk ; 2.500 ; -0.122 ; 3.177 ; -; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.263 ; -; -0.663 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.264 ; -; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.261 ; -; -0.663 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.261 ; -; -0.663 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.277 ; -; -0.663 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.255 ; -; -0.663 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.248 ; -; -0.663 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; -; -0.663 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; -; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.260 ; -; -0.663 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.269 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[23] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.270 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.279 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.264 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; clk ; clk ; 2.500 ; -0.011 ; 3.285 ; -; -0.663 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.225 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.265 ; -; -0.662 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.257 ; -; -0.662 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.272 ; -; -0.662 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.278 ; -; -0.662 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.250 ; -; -0.662 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.270 ; -; -0.662 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.282 ; -; -0.662 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.281 ; -; -0.662 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; -; -0.662 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.236 ; -; -0.662 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.247 ; -; -0.662 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; -; -0.662 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[5] ; clk ; clk ; 2.500 ; -0.077 ; 3.108 ; -; -0.662 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[2] ; clk ; clk ; 2.500 ; -0.077 ; 3.108 ; -; -0.662 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.261 ; -; -0.662 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.072 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.263 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[28] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; clk ; clk ; 2.500 ; -0.033 ; 3.266 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.270 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[8] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.227 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[4] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.661 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.246 ; -; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.257 ; -; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; -; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.250 ; -; -0.661 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.250 ; -; -0.661 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.250 ; -; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.261 ; -; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.259 ; -; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.266 ; -; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.269 ; -; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.244 ; -; -0.661 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.262 ; -; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.265 ; -; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.258 ; -; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.261 ; -; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.269 ; -; -0.661 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.072 ; -; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; -; -0.661 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[22] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.245 ; -; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; clk ; clk ; 2.500 ; -0.034 ; 3.261 ; -; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; clk ; clk ; 2.500 ; -0.043 ; 3.253 ; -; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.210 ; -; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.210 ; -; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.211 ; -; -0.660 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.261 ; -; -0.660 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.267 ; -; -0.660 ; vx_d_e_reg|b_reg_data[4] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.213 ; -; -0.660 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.250 ; -; -0.660 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.250 ; -; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.245 ; -; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; -; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; -; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; -; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; -; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.244 ; -; -0.660 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|rs1[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.226 ; -; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.251 ; -; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.276 ; -; -0.660 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; -; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.256 ; -; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.253 ; -; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.240 ; -; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.215 ; -; -0.660 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.258 ; -; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; -; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; -; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; -; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.261 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; clk ; clk ; 2.500 ; -0.038 ; 3.255 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[18] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[14] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[12] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; -; -0.660 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.111 ; 2.219 ; -; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.216 ; -; -0.660 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.111 ; 2.219 ; -; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; -; -0.659 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.208 ; -; -0.659 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.254 ; -; -0.659 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.269 ; -; -0.659 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.263 ; -; -0.659 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; -; -0.659 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.273 ; -; -0.659 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; -; -0.659 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.225 ; -; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.251 ; -; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; -; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.244 ; -; -0.659 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.248 ; -; -0.659 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.248 ; -; -0.659 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.260 ; -; -0.659 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.257 ; -; -0.659 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; -; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; -; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; -; -0.659 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; -; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.050 ; 3.245 ; -; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; -; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.276 ; -; -0.658 ; vx_d_e_reg|b_reg_data[28] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.207 ; -; -0.658 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.214 ; -; -0.658 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.215 ; -; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.242 ; -; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.278 ; -; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.253 ; -; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.242 ; -; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; -; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.247 ; -; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.262 ; -; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; -; -0.658 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[2] ; clk ; clk ; 2.500 ; -0.122 ; 3.172 ; -; -0.658 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; -; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.249 ; -; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; -; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.254 ; -; -0.658 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.272 ; -; -0.658 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; -; -0.658 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.254 ; -; -0.658 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.213 ; -; -0.658 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.245 ; -; -0.658 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[29] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.658 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; -; -0.658 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; -; -0.658 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[30] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.243 ; -; -0.658 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[10] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.261 ; -; -0.658 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.220 ; -; -0.658 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.087 ; 3.207 ; -; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.258 ; -; -0.657 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; -; -0.657 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.265 ; -; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; -; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.251 ; -; -0.657 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.263 ; -; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.256 ; -; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.236 ; -; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.249 ; -; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.258 ; -; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.242 ; -; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.259 ; -; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.238 ; -; -0.657 ; vx_d_e_reg|b_reg_data[16] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.210 ; -; -0.657 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.260 ; -; -0.657 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.249 ; -; -0.657 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[27] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; -; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.258 ; -; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; -; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.255 ; -; -0.657 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.275 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[26] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[31] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[9] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[6] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[3] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.657 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.067 ; -; -0.657 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.211 ; -; -0.657 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.250 ; -; -0.656 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.250 ; -; -0.656 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.206 ; -; -0.656 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.207 ; -; -0.656 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.060 ; 3.228 ; -; -0.656 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.060 ; 3.227 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.280 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; -; -0.656 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.271 ; -; -0.656 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.259 ; -; -0.656 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.163 ; -; -0.656 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.206 ; -; -0.656 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; -; -0.656 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.239 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; -; -0.656 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[26] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.123 ; -; -0.656 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.123 ; -; -0.656 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.218 ; -; -0.656 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.270 ; -; -0.656 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.267 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[25] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[27] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[29] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.271 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[24] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[16] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.270 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.256 ; -; -0.656 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.079 ; 3.076 ; -; -0.656 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.067 ; -; -0.656 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.079 ; 3.076 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.244 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; clk ; clk ; 2.500 ; -0.049 ; 3.244 ; -; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.052 ; 3.250 ; -; -0.655 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.204 ; -; -0.655 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.060 ; 3.225 ; -; -0.655 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.246 ; -; -0.655 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.258 ; -; -0.655 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.256 ; -; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.234 ; -; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.239 ; -; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.248 ; -; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.236 ; -; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; -; -0.655 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.253 ; -; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.238 ; -; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.259 ; -; -0.655 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.241 ; -; -0.655 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; -; -0.655 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.246 ; -; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.261 ; -; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.263 ; -; -0.655 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.272 ; -; -0.655 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[17] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; clk ; clk ; 2.500 ; -0.034 ; 3.258 ; -; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.275 ; -; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.654 ; vx_d_e_reg|rd[1] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; -; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.654 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.210 ; -; -0.654 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.244 ; -; -0.654 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.242 ; -; -0.654 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.210 ; -; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.217 ; -; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.217 ; -; -0.654 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.270 ; -; -0.654 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.271 ; -; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.064 ; -; -0.654 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.275 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[21] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[20] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[19] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[15] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[13] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; -; -0.654 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.091 ; 2.234 ; -; -0.654 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_three|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.229 ; -; -0.654 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; vx_fetch|VX_Warp_one|real_PC[14] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.235 ; -; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.209 ; -; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.210 ; -; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; -; -0.653 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; -; -0.653 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; -; -0.653 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.237 ; -; -0.653 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.238 ; -; -0.653 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.254 ; -; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.265 ; -; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.266 ; -; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.255 ; -; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; -; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.253 ; -; -0.653 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.254 ; -; -0.653 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.251 ; -; -0.653 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.250 ; -; -0.653 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.208 ; -; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.064 ; -; -0.653 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.250 ; -; -0.653 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; -; -0.653 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.080 ; 3.208 ; -; -0.652 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.259 ; -; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.207 ; -; -0.652 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.241 ; -; -0.652 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.256 ; -; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.247 ; -; -0.652 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; -; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; -; -0.652 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.237 ; -; -0.652 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; -; -0.652 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.231 ; -; -0.652 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.247 ; -; -0.652 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; -; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.259 ; -; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.235 ; -; -0.652 ; vx_d_e_reg|b_reg_data[14] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.205 ; -; -0.652 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.266 ; -; -0.652 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[30] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.214 ; -; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.243 ; -; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.254 ; -; -0.652 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.258 ; -; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; -; -0.652 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.269 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.244 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.028 ; 3.269 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.258 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[1] ; clk ; clk ; 2.500 ; -0.080 ; 3.208 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; -; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.262 ; -; -0.651 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.201 ; -; -0.651 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.202 ; -; -0.651 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.261 ; -; -0.651 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.246 ; -; -0.651 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.651 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; -; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.265 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.235 ; -; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.226 ; -; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; -; -0.651 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.246 ; -; -0.651 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; -; -0.651 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.270 ; -; -0.651 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.217 ; -; -0.651 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.217 ; -; -0.651 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.651 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.254 ; -; -0.651 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.165 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[31] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[28] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[23] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[24] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[22] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.651 ; vx_f_d_reg|instruction[0] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.123 ; -; -0.651 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.210 ; -; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; -; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.250 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.237 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; clk ; clk ; 2.500 ; -0.034 ; 3.252 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; clk ; clk ; 2.500 ; -0.049 ; 3.237 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.256 ; -; -0.651 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[0] ; clk ; clk ; 2.500 ; -0.081 ; 3.205 ; -; -0.650 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.199 ; -; -0.650 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.207 ; -; -0.650 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.206 ; -; -0.650 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.650 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.650 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.252 ; -; -0.650 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.241 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.234 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.245 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.234 ; -; -0.650 ; vx_d_e_reg|a_reg_data[5] ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.084 ; 3.204 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; clk ; clk ; 2.500 ; -0.082 ; 3.188 ; -; -0.650 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.229 ; -; -0.650 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.245 ; -; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.250 ; -; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.248 ; -; -0.650 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.248 ; -; -0.650 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[25] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; -; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.247 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.243 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; clk ; clk ; 2.500 ; -0.049 ; 3.237 ; -; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.256 ; -; -0.649 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.204 ; -; -0.649 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.251 ; -; -0.649 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.045 ; 3.241 ; -; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; -; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.243 ; -; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.248 ; -; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; -; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.224 ; -; -0.649 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.649 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.156 ; -; -0.649 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.247 ; -; -0.649 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.202 ; -; -0.649 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.246 ; -; -0.649 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; -; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.246 ; -; -0.649 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; -; -0.649 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.168 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; clk ; clk ; 2.500 ; -0.039 ; 3.245 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.256 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.023 ; 3.262 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[21] ; clk ; clk ; 2.500 ; -0.034 ; 3.112 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[3] ; clk ; clk ; 2.500 ; -0.034 ; 3.112 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; clk ; clk ; 2.500 ; -0.032 ; 3.264 ; -; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; -; -0.648 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.205 ; -; -0.648 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.204 ; -; -0.648 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.236 ; -; -0.648 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.060 ; 3.257 ; -; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; -; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; -; -0.648 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.243 ; -; -0.648 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.272 ; -; -0.648 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; -; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.231 ; -; -0.648 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.237 ; -; -0.648 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.237 ; -; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.240 ; -; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.253 ; -; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.256 ; -; -0.648 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; -; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.245 ; -; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.248 ; -; -0.648 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.175 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; clk ; clk ; 2.500 ; -0.061 ; 3.217 ; -; -0.648 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.203 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[19] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[2] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; -; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.259 ; -; -0.647 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.202 ; -; -0.647 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.257 ; -; -0.647 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.255 ; -; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.254 ; -; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.255 ; -; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.245 ; -; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; -; -0.647 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.238 ; -; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.239 ; -; -0.647 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[14] ; clk ; clk ; 2.500 ; -0.078 ; 3.200 ; -; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.249 ; -; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.250 ; -; -0.647 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.243 ; -; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; -; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.263 ; -; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.247 ; -; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.243 ; -; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.230 ; -; -0.647 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.206 ; -; -0.647 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.238 ; -; -0.647 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.246 ; -; -0.647 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.202 ; -; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; -; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; -; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.025 ; 3.274 ; -; -0.647 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[22] ; clk ; clk ; 2.500 ; -0.036 ; 3.243 ; -; -0.647 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.208 ; -; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; -; -0.647 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.091 ; 2.227 ; -; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.262 ; -; -0.646 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; -; -0.646 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.197 ; -; -0.646 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.196 ; -; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; -; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; -; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; -; -0.646 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.202 ; -; -0.646 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.236 ; -; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.229 ; -; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.252 ; -; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; -; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.247 ; -; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.231 ; -; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.238 ; -; -0.646 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.200 ; -; -0.646 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.204 ; -; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; -; -0.646 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.209 ; -; -0.646 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.209 ; -; -0.646 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.174 ; -; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; clk ; clk ; 2.500 ; -0.076 ; 3.203 ; -; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; clk ; clk ; 2.500 ; -0.043 ; 3.239 ; -; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; clk ; clk ; 2.500 ; -0.011 ; 3.270 ; -; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; clk ; clk ; 2.500 ; -0.039 ; 3.259 ; -; -0.645 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.240 ; -; -0.645 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.234 ; -; -0.645 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; -; -0.645 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.255 ; -; -0.645 ; vx_d_e_reg|a_reg_data[3] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.072 ; 3.209 ; -; -0.645 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.194 ; -; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.224 ; -; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.251 ; -; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; -; -0.645 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; -; -0.645 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.229 ; -; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.238 ; -; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; -; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.247 ; -; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.248 ; -; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.234 ; -; -0.645 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; -; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.245 ; -; -0.645 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.243 ; -; -0.645 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.251 ; -; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.243 ; -; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.227 ; -; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; clk ; clk ; 2.500 ; -0.040 ; 3.257 ; -; -0.645 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.116 ; -; -0.645 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.083 ; 3.199 ; -; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; -; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.201 ; -; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; -; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.201 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[11] ; clk ; clk ; 2.500 ; -0.024 ; 3.107 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[7] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[5] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.245 ; -; -0.644 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.196 ; -; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.234 ; -; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.257 ; -; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.245 ; -; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.223 ; -; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.246 ; -; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.225 ; -; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.206 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.246 ; -; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.235 ; -; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.261 ; -; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.245 ; -; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.261 ; -; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.242 ; -; -0.644 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; -; -0.644 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.206 ; -; -0.644 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.238 ; -; -0.644 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.038 ; 3.241 ; -; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.198 ; -; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; -; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.199 ; -; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.198 ; -; -0.643 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.193 ; -; -0.643 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.194 ; -; -0.643 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.232 ; -; -0.643 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; -; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.026 ; 3.263 ; -; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; clk ; clk ; 2.500 ; -0.033 ; 3.244 ; -; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.263 ; -; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; -; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; -; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.236 ; -; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.236 ; -; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.232 ; -; -0.643 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.246 ; -; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.248 ; -; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.251 ; -; -0.643 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.226 ; -; -0.643 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.195 ; -; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.245 ; -; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.243 ; -; -0.643 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.271 ; -; -0.643 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.250 ; -; -0.642 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.197 ; -; -0.642 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.191 ; -; -0.642 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.249 ; -; -0.642 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; -; -0.642 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.231 ; -; -0.642 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[6] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; -; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.233 ; -; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.232 ; -; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.223 ; -; -0.642 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.244 ; -; -0.642 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.233 ; -; -0.642 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.256 ; -; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.232 ; -; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.255 ; -; -0.642 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.242 ; -; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.243 ; -; -0.642 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.243 ; -; -0.642 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.239 ; -; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.226 ; -; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.235 ; -; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.249 ; -; -0.642 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.237 ; -; -0.642 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.200 ; -; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.248 ; -; -0.642 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.258 ; -; -0.642 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[14] ; clk ; clk ; 2.500 ; -0.027 ; 3.112 ; -; -0.642 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[8] ; clk ; clk ; 2.500 ; -0.027 ; 3.112 ; -; -0.641 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.197 ; -; -0.641 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.248 ; -; -0.641 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.242 ; -; -0.641 ; vx_f_d_reg|instruction[0] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.242 ; -; -0.641 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.243 ; -+--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ - -Path #1: Setup slack is -0.962 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.562 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.962 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.489 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.221 ; 89 ; 1.092 ; 1.129 ; -; Cell ; ; 6 ; 0.135 ; 5 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; 6.562 ; 2.489 ; ; ; ; ; ; data path ; -; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; -; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; -; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; -; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.533 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; -; 6.562 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.562 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.562 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #2: Setup slack is -0.960 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.561 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.960 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.488 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.220 ; 89 ; 1.092 ; 1.128 ; -; Cell ; ; 6 ; 0.135 ; 5 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; 6.561 ; 2.488 ; ; ; ; ; ; data path ; -; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; -; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; -; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; -; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.532 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; -; 6.561 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; -; 6.561 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; -; 6.561 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #3: Setup slack is -0.946 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.548 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.946 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.475 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.209 ; 89 ; 1.092 ; 1.117 ; -; Cell ; ; 6 ; 0.133 ; 5 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; -; 6.548 ; 2.475 ; ; ; ; ; ; data path ; -; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; -; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; -; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; -; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.521 ; 1.117 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|dataf ; -; 6.548 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; -; 6.548 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; -; 6.548 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #4: Setup slack is -0.932 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.480 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.932 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.482 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.963 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.480 ; 3.482 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.452 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.480 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.480 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.480 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #5: Setup slack is -0.932 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.481 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.932 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.483 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.964 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.481 ; 3.483 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.453 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.481 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.481 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.481 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #6: Setup slack is -0.931 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.478 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.931 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.480 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.961 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.478 ; 3.480 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.450 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.478 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.478 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.478 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #7: Setup slack is -0.924 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.510 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.924 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.512 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.959 ; 84 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.432 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.510 ; 3.512 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.448 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.510 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.510 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.510 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #8: Setup slack is -0.913 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.512 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.913 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.514 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.934 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.459 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.512 ; 3.514 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.123 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.151 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.157 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.437 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.512 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.512 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.512 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #9: Setup slack is -0.910 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.482 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.910 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.484 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.025 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.482 ; 3.484 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.455 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.482 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.482 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.482 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #10: Setup slack is -0.909 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.457 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.909 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.459 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.397 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.457 ; 3.459 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.430 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.457 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.457 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.457 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #11: Setup slack is -0.898 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.508 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.898 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.510 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.051 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.508 ; 3.510 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.482 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.508 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.508 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.508 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #12: Setup slack is -0.898 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.500 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.898 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.502 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.920 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.461 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.500 ; 3.502 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.129 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.159 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.165 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.425 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.500 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.500 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.500 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #13: Setup slack is -0.895 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.365 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.895 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.367 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.907 ; 86 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.365 ; 3.367 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.365 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #14: Setup slack is -0.893 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.486 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.893 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.488 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.972 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.486 ; 3.488 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.404 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.486 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.486 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.486 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #15: Setup slack is -0.887 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.474 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.887 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.476 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.016 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.474 ; 3.476 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.446 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.474 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #16: Setup slack is -0.887 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.474 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.887 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.476 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.016 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.474 ; 3.476 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.446 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.474 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #17: Setup slack is -0.886 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.481 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.886 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.483 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 82 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.496 ; 14 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.481 ; 3.483 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.389 ; 0.472 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.463 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.467 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.361 ; 0.894 ; FF ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.481 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.481 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.481 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #18: Setup slack is -0.883 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.478 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.883 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.480 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 82 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.493 ; 14 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.478 ; 3.480 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.389 ; 0.472 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.463 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.467 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.361 ; 0.894 ; FF ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.478 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.478 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.478 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #19: Setup slack is -0.878 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.450 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.878 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.452 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.046 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.450 ; 3.452 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.423 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.450 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.450 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.450 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #20: Setup slack is -0.875 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.423 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.875 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.425 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.909 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.423 ; 3.425 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.395 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.423 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #21: Setup slack is -0.875 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.424 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.875 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.426 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.424 ; 3.426 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.396 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.424 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #22: Setup slack is -0.874 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.421 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.874 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.423 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.907 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.421 ; 3.423 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.393 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.421 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #23: Setup slack is -0.870 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.870 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.988 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.415 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.442 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #24: Setup slack is -0.869 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.443 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.869 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.445 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.967 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 10 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.443 ; 3.445 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.416 ; 0.984 ; FF ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.443 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.443 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.443 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #25: Setup slack is -0.869 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.869 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.967 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.356 ; 10 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.416 ; 0.984 ; FF ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.442 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #26: Setup slack is -0.867 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.453 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.867 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.455 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.905 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.428 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.453 ; 3.455 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.391 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.453 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #27: Setup slack is -0.866 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.476 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.866 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.478 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.072 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.476 ; 3.478 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.450 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.476 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.476 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.476 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #28: Setup slack is -0.866 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.453 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.866 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.455 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.994 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.453 ; 3.455 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.426 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.453 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #29: Setup slack is -0.865 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.453 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.865 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.455 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.994 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.453 ; 3.455 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.426 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.453 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #30: Setup slack is -0.861 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.454 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.861 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.456 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.993 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.454 ; 3.456 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.372 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.454 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.454 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.454 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #31: Setup slack is -0.858 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.468 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.858 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.470 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.014 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.468 ; 3.470 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.442 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.468 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.468 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.468 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #32: Setup slack is -0.855 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.855 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.037 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.414 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.442 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #33: Setup slack is -0.855 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.855 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.037 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.414 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.442 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #34: Setup slack is -0.855 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.855 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.846 ; 83 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.477 ; 14 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.335 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.442 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #35: Setup slack is -0.854 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.455 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.854 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.457 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.918 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.418 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.455 ; 3.457 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.368 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.455 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.455 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.455 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #36: Setup slack is -0.854 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.441 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.854 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.443 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.846 ; 83 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.476 ; 14 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.441 ; 3.443 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.335 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.441 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.441 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.441 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #37: Setup slack is -0.853 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.446 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.853 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.448 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.935 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.446 ; 3.448 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.364 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.446 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.446 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.446 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #38: Setup slack is -0.852 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.400 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.852 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.402 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.400 ; 3.402 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.373 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.400 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.400 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.400 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #39: Setup slack is -0.852 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.451 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.852 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.453 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.871 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.451 ; 3.453 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.062 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.090 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.096 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.376 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.451 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.451 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.451 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #40: Setup slack is -0.849 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.397 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.849 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.399 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.894 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.397 ; 3.399 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.369 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.397 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #41: Setup slack is -0.849 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.398 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.849 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.400 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.895 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.398 ; 3.400 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.370 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.398 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #42: Setup slack is -0.848 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.395 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.848 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.892 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.395 ; 3.397 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.367 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.395 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #43: Setup slack is -0.848 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.848 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.900 ; 86 ; 0.590 ; 0.986 ; -; Cell ; ; 10 ; 0.336 ; 10 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.353 ; 3.361 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.873 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; -; 3.993 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.999 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.635 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.662 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.666 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.652 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; -; 5.679 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; -; 5.684 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; -; 6.274 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; -; 6.353 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #44: Setup slack is -0.847 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.434 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.847 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.436 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.979 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.434 ; 3.436 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.406 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.434 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #45: Setup slack is -0.847 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.434 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.847 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.436 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.979 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.434 ; 3.436 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.406 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.434 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #46: Setup slack is -0.846 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.418 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.846 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.420 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.954 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.418 ; 3.420 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.391 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.418 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #47: Setup slack is -0.844 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.439 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.844 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.441 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.885 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.434 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.439 ; 3.441 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.314 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.439 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #48: Setup slack is -0.844 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.416 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.844 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.418 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.973 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.416 ; 3.418 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.389 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.416 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #49: Setup slack is -0.844 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.436 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.844 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.438 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.926 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.436 ; 3.438 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.357 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.436 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.436 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.436 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #50: Setup slack is -0.843 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.413 ; -; Slack ; -0.843 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.141 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.872 ; 88 ; 0.666 ; 0.817 ; -; Cell ; ; 8 ; 0.267 ; 8 ; 0.000 ; 0.112 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.256 ; 3.264 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.868 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; -; 3.980 ; 0.112 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.986 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.663 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.690 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.694 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.406 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; -; 5.434 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; -; 5.439 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; -; 6.256 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; -; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #51: Setup slack is -0.843 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.449 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.843 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.451 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.872 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.458 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.449 ; 3.451 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.169 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.196 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.373 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.449 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #52: Setup slack is -0.842 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.842 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.924 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.363 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #53: Setup slack is -0.842 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.390 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.842 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.392 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.923 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.390 ; 3.392 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.362 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.390 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #54: Setup slack is -0.842 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.437 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.842 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.439 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.885 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.432 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.437 ; 3.439 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.314 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.437 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.437 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.437 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #55: Setup slack is -0.842 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.435 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.842 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.437 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.977 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.435 ; 3.437 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.409 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.435 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #56: Setup slack is -0.841 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.388 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.841 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.390 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.921 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.388 ; 3.390 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.360 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.388 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #57: Setup slack is -0.841 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.427 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.841 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.429 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.890 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.418 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.427 ; 3.429 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.365 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.427 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.427 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.427 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #58: Setup slack is -0.841 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.449 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.841 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.451 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.872 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.458 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.449 ; 3.451 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.169 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.196 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.373 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.449 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #59: Setup slack is -0.841 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.435 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.841 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.437 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.977 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.435 ; 3.437 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.409 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.435 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #60: Setup slack is -0.838 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.838 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.853 ; 86 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.308 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #61: Setup slack is -0.837 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.439 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.837 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.441 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.857 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.462 ; 13 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.439 ; 3.441 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.098 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.104 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.364 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.439 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #62: Setup slack is -0.837 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.437 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.837 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.104 ; ; ; ; ; ; -; Data Delay ; 2.367 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.094 ; 88 ; 0.965 ; 1.129 ; -; Cell ; ; 6 ; 0.141 ; 6 ; 0.000 ; 0.062 ; -; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; -; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; 6.437 ; 2.367 ; ; ; ; ; ; data path ; -; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; -; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; -; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; -; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.408 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; -; 6.437 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.437 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.437 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #63: Setup slack is -0.836 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.431 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.836 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.433 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 82 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.484 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.431 ; 3.433 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.368 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.448 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.452 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.306 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.431 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.431 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.431 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #64: Setup slack is -0.836 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.423 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.836 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.425 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.965 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.423 ; 3.425 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.397 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.423 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #65: Setup slack is -0.835 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.436 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.835 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.104 ; ; ; ; ; ; -; Data Delay ; 2.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.093 ; 88 ; 0.965 ; 1.128 ; -; Cell ; ; 6 ; 0.141 ; 6 ; 0.000 ; 0.062 ; -; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; -; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; 6.436 ; 2.366 ; ; ; ; ; ; data path ; -; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; -; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; -; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; -; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.407 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; -; 6.436 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; -; 6.436 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; -; 6.436 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #66: Setup slack is -0.834 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.420 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.834 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.422 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.919 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.383 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.420 ; 3.422 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.358 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.420 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.420 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.420 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #67: Setup slack is -0.834 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.421 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.834 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.423 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.015 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.421 ; 3.423 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.394 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.421 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #68: Setup slack is -0.834 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.429 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.834 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.431 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 82 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.482 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.429 ; 3.431 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.368 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.448 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.452 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.306 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.429 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.429 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.429 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #69: Setup slack is -0.834 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.444 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.834 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.446 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.980 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.444 ; 3.446 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.418 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.444 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.444 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.444 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #70: Setup slack is -0.833 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.421 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.833 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.423 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.015 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.421 ; 3.423 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.394 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.421 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #71: Setup slack is -0.833 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.405 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.833 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.407 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.944 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.405 ; 3.407 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.378 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.405 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.405 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.405 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #72: Setup slack is -0.833 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.388 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.833 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.390 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.890 ; 85 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.388 ; 3.390 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.359 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.388 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #73: Setup slack is -0.833 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.388 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.833 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.390 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.889 ; 85 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.388 ; 3.390 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.358 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.388 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #74: Setup slack is -0.832 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.442 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.832 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.444 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.999 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.442 ; 3.444 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.416 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.442 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #75: Setup slack is -0.831 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.385 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.831 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.387 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.886 ; 85 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.385 ; 3.387 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.355 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.385 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #76: Setup slack is -0.830 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.469 ; -; Data Required Time ; 5.639 ; -; Slack ; -0.830 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.094 ; ; ; ; ; ; -; Data Delay ; 2.410 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.045 ; 85 ; 0.551 ; 0.786 ; -; Cell ; ; 8 ; 0.226 ; 9 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; -; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; 6.469 ; 2.410 ; ; ; ; ; ; data path ; -; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; -; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; -; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; -; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.410 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; -; 6.469 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; -; 6.469 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; -; 6.469 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #77: Setup slack is -0.829 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.422 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.829 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.424 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.422 ; 3.424 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.340 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.422 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.422 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.422 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #78: Setup slack is -0.828 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.828 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.349 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.243 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #79: Setup slack is -0.827 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.420 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.827 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.422 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.920 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.381 ; 11 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.420 ; 3.422 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.338 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.420 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.420 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.420 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #80: Setup slack is -0.827 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.827 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.349 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.243 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #81: Setup slack is -0.826 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.374 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.826 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.376 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.872 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.383 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.374 ; 3.376 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.347 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.374 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.374 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.374 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #82: Setup slack is -0.826 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.413 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.826 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.415 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.413 ; 3.415 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.386 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.413 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #83: Setup slack is -0.826 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.425 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.826 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.427 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.967 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.425 ; 3.427 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.399 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.425 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.425 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.425 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #84: Setup slack is -0.826 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.377 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.826 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.379 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.881 ; 85 ; 0.108 ; 0.935 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.377 ; 3.379 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.349 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.377 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.377 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.377 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #85: Setup slack is -0.825 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.413 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.825 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.415 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.413 ; 3.415 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.386 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.413 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #86: Setup slack is -0.825 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.398 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.825 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.400 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.995 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.283 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.398 ; 3.400 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.406 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.410 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.371 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.398 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #87: Setup slack is -0.824 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.423 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.824 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.425 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.855 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.423 ; 3.425 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.034 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.062 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.068 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.348 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.423 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.423 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.423 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #88: Setup slack is -0.824 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.398 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.824 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.400 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.995 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.283 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.398 ; 3.400 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.406 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.410 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.371 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.398 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #89: Setup slack is -0.824 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.424 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.824 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.426 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.424 ; 3.426 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.331 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.424 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.424 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.424 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #90: Setup slack is -0.823 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.410 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.823 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.412 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.945 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.410 ; 3.412 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.382 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.410 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #91: Setup slack is -0.823 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.410 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.823 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.412 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.945 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.410 ; 3.412 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.382 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.410 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #92: Setup slack is -0.823 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.417 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.823 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.419 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.957 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.417 ; 3.419 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.389 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.417 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.417 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.417 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #93: Setup slack is -0.822 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.409 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.822 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.411 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.932 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 10 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.409 ; 3.411 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.382 ; 0.859 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.409 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.166 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #94: Setup slack is -0.822 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.451 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.822 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 2.379 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.046 ; 86 ; 0.403 ; 0.979 ; -; Cell ; ; 8 ; 0.194 ; 8 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; 6.451 ; 2.379 ; ; ; ; ; ; data path ; -; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; -; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; -; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; -; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.989 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; -; 6.392 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; -; 6.451 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; -; 6.451 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; -; 6.451 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #95: Setup slack is -0.821 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.408 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.821 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.410 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.964 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.408 ; 3.410 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.380 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.408 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #96: Setup slack is -0.821 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.408 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.821 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.410 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.964 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.408 ; 3.410 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.380 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.408 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #97: Setup slack is -0.821 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.431 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.821 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.433 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.970 ; 87 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.431 ; 3.433 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.405 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.431 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.431 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.431 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #98: Setup slack is -0.821 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.821 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.373 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.876 ; 85 ; 0.108 ; 0.930 ; -; Cell ; ; 12 ; 0.376 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.371 ; 3.373 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.344 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.371 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #99: Setup slack is -0.821 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.423 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.821 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.104 ; ; ; ; ; ; -; Data Delay ; 2.353 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 2.082 ; 88 ; 0.965 ; 1.117 ; -; Cell ; ; 6 ; 0.139 ; 6 ; 0.000 ; 0.062 ; -; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; -; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; -; 6.423 ; 2.353 ; ; ; ; ; ; data path ; -; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; -; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; -; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; -; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.396 ; 1.117 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|dataf ; -; 6.423 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; -; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #100: Setup slack is -0.820 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.820 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.888 ; 86 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.341 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.369 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #101: Setup slack is -0.820 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.368 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.820 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.370 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 86 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.368 ; 3.370 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.340 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.368 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #102: Setup slack is -0.820 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.392 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.820 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.394 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.985 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.392 ; 3.394 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.509 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.365 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.392 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #103: Setup slack is -0.819 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.367 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.819 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.369 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.348 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.367 ; 3.369 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.340 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.367 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #104: Setup slack is -0.819 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.366 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.819 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.368 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.885 ; 86 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.366 ; 3.368 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.338 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.366 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #105: Setup slack is -0.819 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.373 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.819 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.375 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.875 ; 85 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.373 ; 3.375 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.344 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.373 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.373 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.373 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #106: Setup slack is -0.818 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.424 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.818 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.426 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.964 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.424 ; 3.426 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.396 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.424 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #107: Setup slack is -0.817 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.390 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.817 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.392 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.937 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.390 ; 3.392 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.398 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.402 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.363 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.390 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #108: Setup slack is -0.816 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.390 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.816 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.392 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.937 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.390 ; 3.392 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.398 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.402 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.363 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.390 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #109: Setup slack is -0.816 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.409 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.816 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.411 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.891 ; 85 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.409 ; 3.411 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.327 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.409 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #110: Setup slack is -0.815 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.387 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.815 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.389 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.966 ; 88 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.387 ; 3.389 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.472 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.499 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.504 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.360 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.387 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #111: Setup slack is -0.813 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.422 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.813 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.424 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.422 ; 3.424 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.183 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.212 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.218 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.346 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.422 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #112: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.398 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.400 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.398 ; 3.400 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.336 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.398 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #113: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.404 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.406 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.947 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.404 ; 3.406 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.325 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.404 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #114: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.407 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.409 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 82 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.494 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.407 ; 3.409 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.344 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.428 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.282 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.407 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.407 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.407 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #115: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.838 ; 86 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.282 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #116: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.396 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.398 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.917 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.396 ; 3.398 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.367 ; 0.844 ; FF ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.396 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #117: Setup slack is -0.812 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.422 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.812 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.424 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.422 ; 3.424 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.173 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.200 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.206 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.344 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.422 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #118: Setup slack is -0.810 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.403 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.810 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.405 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.998 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.403 ; 3.405 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.377 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.403 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #119: Setup slack is -0.810 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.405 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.810 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.407 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.474 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.405 ; 3.407 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.342 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.426 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.280 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.405 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #120: Setup slack is -0.810 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.405 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.810 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.407 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 82 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.492 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.405 ; 3.407 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.344 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.428 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.282 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.405 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #121: Setup slack is -0.810 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.397 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.810 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.399 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.935 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.397 ; 3.399 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.369 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.397 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #122: Setup slack is -0.810 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.397 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.810 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.399 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.935 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.397 ; 3.399 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.369 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.397 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #123: Setup slack is -0.809 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.411 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.809 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.413 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.451 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.411 ; 3.413 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.040 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.070 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.076 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.336 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.411 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.411 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.411 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #124: Setup slack is -0.809 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.403 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.809 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.405 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.998 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.403 ; 3.405 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.377 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.403 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #125: Setup slack is -0.809 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.381 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.809 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.383 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.950 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.381 ; 3.383 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.466 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.493 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.498 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.354 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.381 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.381 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.381 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #126: Setup slack is -0.808 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.403 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.808 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.405 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.403 ; 3.405 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.342 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.426 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.280 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.403 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.403 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.403 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #127: Setup slack is -0.808 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.418 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.808 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.420 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 3.011 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 8 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.418 ; 3.420 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.392 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.418 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #128: Setup slack is -0.806 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.405 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.806 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.407 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.429 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.405 ; 3.407 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.016 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.044 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.050 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.330 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.405 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #129: Setup slack is -0.805 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.805 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.867 ; 87 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.275 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #130: Setup slack is -0.804 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.396 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.804 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.398 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.396 ; 3.398 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.317 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.396 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #131: Setup slack is -0.804 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.804 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.986 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.365 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.391 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #132: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.404 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.406 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.927 ; 86 ; 0.119 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.404 ; 3.406 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.271 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.297 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.303 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.317 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.404 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #133: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.396 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.398 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.932 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.396 ; 3.398 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.314 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.396 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #134: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.413 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.415 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.992 ; 88 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.413 ; 3.415 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.387 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.413 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #135: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.387 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.389 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.845 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.423 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.387 ; 3.389 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.295 ; 0.803 ; FF ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.387 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #136: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.363 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #137: Setup slack is -0.803 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.803 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.363 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #138: Setup slack is -0.802 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.395 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.802 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.940 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.395 ; 3.397 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.369 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.395 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #139: Setup slack is -0.802 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.389 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.802 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.391 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.923 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.389 ; 3.391 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.362 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.389 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #140: Setup slack is -0.802 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.416 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.802 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.418 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.958 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.416 ; 3.418 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.390 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.416 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #141: Setup slack is -0.801 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.395 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.801 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.940 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.395 ; 3.397 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.369 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.395 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #142: Setup slack is -0.801 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.389 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.801 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.391 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.923 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.389 ; 3.391 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.362 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.389 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #143: Setup slack is -0.801 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.400 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.801 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.402 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.400 ; 3.402 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.266 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.400 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.400 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.400 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #144: Setup slack is -0.801 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.801 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.721 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.321 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.349 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #145: Setup slack is -0.801 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.350 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.801 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.352 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.722 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.350 ; 3.352 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.322 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.350 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #146: Setup slack is -0.800 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.387 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.800 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.389 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.942 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.387 ; 3.389 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.360 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.387 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #147: Setup slack is -0.800 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.396 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.800 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.398 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.872 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.396 ; 3.398 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.363 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.396 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.304 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.396 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #148: Setup slack is -0.800 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.348 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.800 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.356 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.736 ; 82 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.348 ; 3.356 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.320 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.348 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #149: Setup slack is -0.800 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.800 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.357 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.737 ; 82 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.349 ; 3.357 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.321 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.349 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #150: Setup slack is -0.800 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.347 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.800 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.719 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.347 ; 3.349 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.319 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.347 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #151: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.387 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.389 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.942 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.387 ; 3.389 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.360 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.387 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #152: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.394 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.396 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 82 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.492 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.394 ; 3.396 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.331 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.411 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.415 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.269 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.394 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.394 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.394 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #153: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.399 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.401 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.399 ; 3.401 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.372 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.399 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #154: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #155: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.734 ; 82 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.346 ; 3.354 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.318 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.346 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #156: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.856 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.325 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.353 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #157: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.806 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.264 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #158: Setup slack is -0.799 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.799 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.806 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.264 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #159: Setup slack is -0.798 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.385 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.798 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.387 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 82 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.473 ; 14 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.385 ; 3.387 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.278 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.385 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #160: Setup slack is -0.798 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.798 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.309 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.391 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #161: Setup slack is -0.798 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.798 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.856 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.325 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.353 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #162: Setup slack is -0.798 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.399 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.798 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.401 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.399 ; 3.401 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.372 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.399 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #163: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 82 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.278 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.384 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #164: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.865 ; 86 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.318 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.345 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #165: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.392 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.394 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 82 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.490 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.392 ; 3.394 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.331 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.411 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.415 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.269 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.392 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #166: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.976 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.356 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.384 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #167: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.976 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.356 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.384 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #168: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.407 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.409 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.976 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.407 ; 3.409 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.381 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.407 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.407 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.407 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #169: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.382 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.384 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.839 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.424 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.382 ; 3.384 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.289 ; 0.797 ; FF ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.382 ; 0.093 ; FF ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.382 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.382 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #170: Setup slack is -0.797 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.351 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.797 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.353 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.854 ; 85 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.351 ; 3.353 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.323 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.351 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #171: Setup slack is -0.796 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.395 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.796 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.899 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.378 ; 11 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.395 ; 3.397 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.006 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.034 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.040 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.320 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.395 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #172: Setup slack is -0.796 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.383 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.796 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.385 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.928 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.383 ; 3.385 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.357 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.383 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.383 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.383 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #173: Setup slack is -0.796 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.796 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #174: Setup slack is -0.796 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.796 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.851 ; 85 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.320 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.349 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #175: Setup slack is -0.795 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.396 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.795 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.398 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.396 ; 3.398 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.266 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.396 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #176: Setup slack is -0.795 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.795 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #177: Setup slack is -0.795 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.378 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.795 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.380 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.920 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.378 ; 3.380 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.350 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.378 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #178: Setup slack is -0.794 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.393 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.794 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.395 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.988 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.393 ; 3.395 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.367 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.393 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.393 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.393 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #179: Setup slack is -0.794 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.395 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.794 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.879 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.395 ; 3.397 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.308 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.395 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #180: Setup slack is -0.793 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.366 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.793 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.368 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.903 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.366 ; 3.368 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.374 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.378 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.339 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.366 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #181: Setup slack is -0.793 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.379 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.793 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.381 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 80 ; 0.192 ; 0.712 ; -; Cell ; ; 14 ; 0.543 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.379 ; 3.381 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.317 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.379 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #182: Setup slack is -0.793 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.793 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.722 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.341 ; 3.349 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.313 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.341 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #183: Setup slack is -0.793 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.342 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.793 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.350 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.723 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.342 ; 3.350 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.314 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.342 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #184: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.392 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.394 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.922 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.350 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.392 ; 3.394 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.299 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.392 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #185: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.366 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.368 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.903 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.366 ; 3.368 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.374 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.378 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.339 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.366 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #186: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.379 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.381 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.379 ; 3.381 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.351 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.379 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #187: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.379 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.381 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.379 ; 3.381 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.351 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.379 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #188: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.385 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.387 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.897 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.369 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.385 ; 3.387 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.303 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.385 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #189: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.378 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.732 ; 81 ; 0.192 ; 0.712 ; -; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.378 ; 3.386 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.316 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.378 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #190: Setup slack is -0.792 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.339 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.792 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.720 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.339 ; 3.347 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.311 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.339 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #191: Setup slack is -0.791 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.393 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.791 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.395 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.393 ; 3.395 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.022 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.052 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.058 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.318 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.393 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.393 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.393 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #192: Setup slack is -0.791 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.385 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.791 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.387 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.978 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.385 ; 3.387 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.357 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.385 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #193: Setup slack is -0.791 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.364 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.791 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.922 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.364 ; 3.366 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.372 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.376 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.337 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.364 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #194: Setup slack is -0.790 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.364 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.790 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.922 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.364 ; 3.366 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.372 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.376 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.337 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.364 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #195: Setup slack is -0.789 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.391 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.789 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.393 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.876 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.391 ; 3.393 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.020 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.049 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.055 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.318 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.391 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #196: Setup slack is -0.789 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.338 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.789 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.340 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.884 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.338 ; 3.340 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.310 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.338 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #197: Setup slack is -0.789 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.337 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.789 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.339 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.337 ; 3.339 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.309 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.337 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #198: Setup slack is -0.789 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.376 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.789 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.378 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.376 ; 3.378 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.349 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.376 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #199: Setup slack is -0.788 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.788 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.881 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.307 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.335 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #200: Setup slack is -0.788 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.376 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.788 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.378 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.376 ; 3.378 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.349 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.376 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #201: Setup slack is -0.788 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.372 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.788 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.374 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.372 ; 3.374 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.344 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.372 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.372 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.372 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #202: Setup slack is -0.787 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.373 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.787 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.375 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.969 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.373 ; 3.375 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.347 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.373 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #203: Setup slack is -0.786 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.392 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.786 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.394 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.985 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.392 ; 3.394 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.364 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #204: Setup slack is -0.786 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.385 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.786 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.387 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.930 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.385 ; 3.387 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.359 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.385 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #205: Setup slack is -0.786 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.381 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.786 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.383 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.824 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.381 ; 3.383 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.318 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.398 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.402 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.256 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.381 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #206: Setup slack is -0.786 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.373 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.786 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.375 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.373 ; 3.375 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.345 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.373 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #207: Setup slack is -0.786 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.373 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.786 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.375 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.373 ; 3.375 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.345 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.373 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #208: Setup slack is -0.785 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.785 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.379 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.718 ; 80 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.536 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.371 ; 3.379 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.309 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.371 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #209: Setup slack is -0.784 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.784 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.864 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.291 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.384 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.384 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.384 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #210: Setup slack is -0.784 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.379 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.784 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.381 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.824 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.437 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.379 ; 3.381 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.318 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.398 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.402 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.256 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.379 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.379 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.379 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #211: Setup slack is -0.783 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.377 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.783 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.379 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.920 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.377 ; 3.379 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.349 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.377 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #212: Setup slack is -0.783 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.783 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.831 ; 87 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.302 ; 9 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.253 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #213: Setup slack is -0.783 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.783 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #214: Setup slack is -0.783 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.783 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #215: Setup slack is -0.783 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.783 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #216: Setup slack is -0.782 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.388 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.782 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.390 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.388 ; 3.390 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.108 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.135 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.141 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.312 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.388 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #217: Setup slack is -0.782 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.421 ; -; Data Required Time ; 5.639 ; -; Slack ; -0.782 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.090 ; ; ; ; ; ; -; Data Delay ; 2.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.018 ; 85 ; 0.551 ; 0.786 ; -; Cell ; ; 8 ; 0.216 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|clk ; -; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; -; 6.421 ; 2.366 ; ; ; ; ; ; data path ; -; 4.187 ; 0.132 ; FF ; uTco ; 1 ; FF_X90_Y148_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|q ; -; 4.230 ; 0.043 ; FF ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]~la_mlab/laboutb[17] ; -; 4.911 ; 0.681 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datad ; -; 4.989 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 4.994 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.780 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.806 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.811 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.362 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; -; 6.421 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; -; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #218: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.367 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.369 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.879 ; 85 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.368 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.367 ; 3.369 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.305 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.367 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #219: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.376 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.378 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.376 ; 3.378 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.313 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.393 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.397 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.251 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.376 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.376 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.376 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #220: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.381 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.383 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.381 ; 3.383 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.298 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.381 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #221: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.791 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.249 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #222: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.791 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.249 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #223: Setup slack is -0.781 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.379 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.781 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.001 ; ; ; ; ; ; -; Data Delay ; 3.416 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.895 ; 85 ; 0.122 ; 0.959 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; -; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; 6.379 ; 3.416 ; ; ; ; ; ; data path ; -; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|q ; -; 3.150 ; 0.060 ; RR ; CELL ; 648 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE~la_lab/laboutt[10] ; -; 4.109 ; 0.959 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|datad ; -; 4.189 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; -; 4.193 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; -; 4.454 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; -; 4.482 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; -; 4.487 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; -; 5.142 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; -; 5.228 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.234 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.357 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.420 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.424 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.199 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.226 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.231 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.353 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.379 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #224: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.388 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.390 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.388 ; 3.390 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.108 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.135 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.141 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.312 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.388 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #225: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.372 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.374 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.855 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.372 ; 3.374 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.293 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.372 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #226: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.361 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.365 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.326 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.353 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #227: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #228: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.414 ; -; Data Required Time ; 5.634 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.108 ; ; ; ; ; ; -; Data Delay ; 2.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.004 ; 86 ; 0.361 ; 0.979 ; -; Cell ; ; 8 ; 0.199 ; 8 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; 6.414 ; 2.342 ; ; ; ; ; ; data path ; -; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; -; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; -; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; -; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.990 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; -; 6.351 ; 0.361 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|datae ; -; 6.414 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|combout ; -; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|d ; -; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y157_N37 ; ; vx_fetch|VX_Warp_one|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #229: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.413 ; -; Data Required Time ; 5.633 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.108 ; ; ; ; ; ; -; Data Delay ; 2.341 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.003 ; 86 ; 0.360 ; 0.979 ; -; Cell ; ; 8 ; 0.199 ; 9 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; -; 6.413 ; 2.341 ; ; ; ; ; ; data path ; -; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; -; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; -; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; -; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.990 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; -; 6.350 ; 0.360 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|datae ; -; 6.413 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|combout ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|d ; -; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N43 ; ; vx_fetch|VX_Warp_two|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #230: Setup slack is -0.780 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.780 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #231: Setup slack is -0.779 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.365 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.779 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.367 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.911 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.365 ; 3.367 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.339 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.365 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #232: Setup slack is -0.779 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.779 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.361 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.365 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.326 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.353 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #233: Setup slack is -0.779 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.374 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.779 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.376 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.374 ; 3.376 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.313 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.393 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.397 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.251 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.374 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.374 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.374 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #234: Setup slack is -0.778 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.361 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.778 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.363 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.956 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.361 ; 3.363 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.334 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.361 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #235: Setup slack is -0.778 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.778 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.927 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.356 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.384 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #236: Setup slack is -0.778 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.778 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.373 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.906 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.371 ; 3.373 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.345 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.371 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #237: Setup slack is -0.778 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.370 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.778 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.372 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.079 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.370 ; 3.372 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.291 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.370 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #238: Setup slack is -0.778 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.326 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.778 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.328 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.699 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.508 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.326 ; 3.328 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.299 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.326 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #239: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.373 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.906 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.371 ; 3.373 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.345 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.371 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #240: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.961 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.466 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.322 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; -; 6.349 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; -; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #241: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #242: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #243: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #244: Setup slack is -0.777 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.325 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.777 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.333 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.714 ; 81 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.492 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.325 ; 3.333 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.298 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.325 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #245: Setup slack is -0.776 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.776 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.925 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.343 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.369 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #246: Setup slack is -0.776 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.363 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.776 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.365 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.954 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.363 ; 3.365 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.336 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.363 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #247: Setup slack is -0.776 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.776 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #248: Setup slack is -0.776 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.776 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.834 ; 85 ; 0.108 ; 0.888 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.303 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; -; 6.330 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #249: Setup slack is -0.776 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.776 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.001 ; ; ; ; ; ; -; Data Delay ; 3.408 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 85 ; 0.114 ; 0.959 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; -; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; 6.371 ; 3.408 ; ; ; ; ; ; data path ; -; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|q ; -; 3.150 ; 0.060 ; RR ; CELL ; 648 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE~la_lab/laboutt[10] ; -; 4.109 ; 0.959 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|datad ; -; 4.189 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; -; 4.193 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; -; 4.454 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; -; 4.482 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; -; 4.487 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; -; 5.142 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; -; 5.228 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.234 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.357 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.420 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.424 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.199 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.226 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.231 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.345 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.371 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #250: Setup slack is -0.775 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.775 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.925 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.343 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.369 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #251: Setup slack is -0.775 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.363 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.775 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.365 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.954 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.363 ; 3.365 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.336 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.363 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #252: Setup slack is -0.775 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.370 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.775 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.372 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 83 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.370 ; 3.372 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.307 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.387 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.391 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.245 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.370 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #253: Setup slack is -0.775 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.368 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.775 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.370 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.908 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.368 ; 3.370 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.341 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.368 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #254: Setup slack is -0.775 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.414 ; -; Data Required Time ; 5.639 ; -; Slack ; -0.775 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.090 ; ; ; ; ; ; -; Data Delay ; 2.359 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.062 ; 87 ; 0.551 ; 0.786 ; -; Cell ; ; 8 ; 0.164 ; 7 ; 0.000 ; 0.059 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|clk ; -; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; -; 6.414 ; 2.359 ; ; ; ; ; ; data path ; -; 4.188 ; 0.133 ; FF ; uTco ; 1 ; FF_X92_Y148_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|q ; -; 4.231 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[9] ; -; 4.956 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|dataf ; -; 4.982 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 4.987 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.773 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.799 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.804 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.355 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; -; 6.414 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; -; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; -; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; -; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #255: Setup slack is -0.773 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.368 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.773 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.370 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 83 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.460 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.368 ; 3.370 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.307 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.387 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.391 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.245 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.368 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #256: Setup slack is -0.772 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.772 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 83 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.252 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.359 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #257: Setup slack is -0.772 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.327 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.772 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.827 ; 85 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.327 ; 3.329 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.298 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.327 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #258: Setup slack is -0.772 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.327 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.772 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.826 ; 85 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.381 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.327 ; 3.329 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.297 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.327 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #259: Setup slack is -0.772 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.772 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.894 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.333 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.359 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #260: Setup slack is -0.771 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.771 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 83 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.252 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.358 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #261: Setup slack is -0.771 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.771 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.935 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.331 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.358 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #262: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 85 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.980 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 6.008 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.014 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.294 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.369 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #263: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.384 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.386 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.979 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.384 ; 3.386 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.358 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.384 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #264: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.898 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.326 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.353 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #265: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.324 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.326 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.823 ; 85 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.381 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.324 ; 3.326 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.294 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.324 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.324 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.324 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #266: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.357 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.359 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.357 ; 3.359 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.331 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.357 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #267: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.371 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.373 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.845 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.371 ; 3.373 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.272 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.299 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.305 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.284 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.371 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #268: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.935 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.331 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.358 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #269: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.326 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.700 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.501 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.318 ; 3.326 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.291 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.318 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #270: Setup slack is -0.770 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[2] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.386 ; -; Data Required Time ; 5.616 ; -; Slack ; -0.770 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.397 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.818 ; 83 ; 0.122 ; 0.775 ; -; Cell ; ; 16 ; 0.459 ; 14 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; -; 6.386 ; 3.397 ; ; ; ; ; ; data path ; -; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; -; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; -; 3.914 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|datae ; -; 3.991 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; -; 3.997 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; -; 4.438 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; -; 4.519 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.524 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.879 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.907 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.913 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.176 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.235 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.241 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.364 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.427 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.431 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.206 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.233 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.238 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.360 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.386 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.386 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.386 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #271: Setup slack is -0.769 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.368 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.769 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.370 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 85 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.368 ; 3.370 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.234 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.368 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #272: Setup slack is -0.769 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.769 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.884 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.260 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.353 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #273: Setup slack is -0.769 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.368 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.769 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.370 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.890 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.368 ; 3.370 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.341 ; 0.817 ; FF ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.368 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #274: Setup slack is -0.768 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.364 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.768 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.351 ; 10 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.364 ; 3.366 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.331 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.360 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.364 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.272 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.364 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #275: Setup slack is -0.768 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.768 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.864 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.270 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.297 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.303 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.282 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.369 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #276: Setup slack is -0.767 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.367 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.767 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.369 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.962 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.367 ; 3.369 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.340 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.367 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #277: Setup slack is -0.767 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.767 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.845 ; 85 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.280 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.359 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.359 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.359 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #278: Setup slack is -0.767 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.767 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.934 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.321 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.348 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.352 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.313 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.340 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #279: Setup slack is -0.767 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.182 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.767 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.184 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.712 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.182 ; 3.184 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.182 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.182 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #280: Setup slack is -0.767 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.369 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.767 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.371 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.892 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.369 ; 3.371 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.546 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.572 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.578 ; 0.006 ; FF ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.342 ; 0.764 ; FF ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.369 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #281: Setup slack is -0.766 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.766 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.287 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.314 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #282: Setup slack is -0.766 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.367 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.766 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.369 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.962 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.367 ; 3.369 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.340 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.367 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #283: Setup slack is -0.766 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.766 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.934 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.321 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.348 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.352 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.313 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.340 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #284: Setup slack is -0.766 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.182 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.766 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.184 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.712 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.182 ; 3.184 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.182 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.182 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #285: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 84 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.352 ; 3.354 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.245 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.352 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #286: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.316 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.818 ; 85 ; 0.108 ; 0.935 ; -; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.316 ; 3.318 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.288 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.316 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #287: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.896 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.332 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.358 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #288: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.919 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.314 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.352 ; 3.354 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.325 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.352 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #289: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.375 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.377 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.987 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.375 ; 3.377 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.567 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.349 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; -; 6.375 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; -; 6.375 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; -; 6.375 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #290: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.822 ; 85 ; 0.108 ; 0.876 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.291 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; -; 6.318 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #291: Setup slack is -0.765 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[2] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.378 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.765 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.389 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.810 ; 83 ; 0.114 ; 0.775 ; -; Cell ; ; 16 ; 0.459 ; 14 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; -; 6.378 ; 3.389 ; ; ; ; ; ; data path ; -; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; -; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; -; 3.914 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|datae ; -; 3.991 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; -; 3.997 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; -; 4.438 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; -; 4.519 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.524 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.879 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.907 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.913 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.176 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.235 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.241 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.364 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.427 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.431 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.206 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.233 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.238 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.352 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.378 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #292: Setup slack is -0.764 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.351 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.764 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.353 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 84 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.427 ; 13 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.351 ; 3.353 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.245 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.351 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #293: Setup slack is -0.764 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.764 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.896 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.332 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.358 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #294: Setup slack is -0.764 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.764 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.919 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.314 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.352 ; 3.354 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.325 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.352 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #295: Setup slack is -0.764 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.347 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.764 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.347 ; 3.349 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.320 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.347 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #296: Setup slack is -0.764 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.370 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.764 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.372 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.370 ; 3.372 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.128 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; -; 6.158 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; -; 6.164 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; -; 6.294 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; -; 6.370 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.370 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.370 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #297: Setup slack is -0.763 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.364 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.763 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.366 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 85 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.364 ; 3.366 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.234 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.364 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #298: Setup slack is -0.763 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.763 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.941 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.318 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.346 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #299: Setup slack is -0.763 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.763 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.121 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.746 ; 84 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.410 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.202 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; -; 6.275 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #300: Setup slack is -0.763 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.763 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.308 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.335 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #301: Setup slack is -0.762 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.376 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.762 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.378 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.921 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.376 ; 3.378 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.350 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.376 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #302: Setup slack is -0.762 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.361 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.762 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.363 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.896 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.361 ; 3.363 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.335 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.361 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #303: Setup slack is -0.762 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.762 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.316 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.343 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.347 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.308 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.335 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #304: Setup slack is -0.762 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.357 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.762 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.359 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.825 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.413 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.357 ; 3.359 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.277 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.357 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #305: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.226 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.360 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #306: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.252 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.345 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #307: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.316 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.343 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.347 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.308 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.335 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #308: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.845 ; 85 ; 0.106 ; 1.302 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.243 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.360 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #309: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.339 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.341 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.881 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.339 ; 3.341 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.312 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.339 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #310: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.352 ; 3.354 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.325 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.352 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #311: Setup slack is -0.761 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.389 ; -; Data Required Time ; 5.628 ; -; Slack ; -0.761 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 2.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.996 ; 86 ; 0.421 ; 0.887 ; -; Cell ; ; 8 ; 0.188 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; 6.389 ; 2.317 ; ; ; ; ; ; data path ; -; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; -; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; -; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.363 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.389 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.628 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #312: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.356 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.358 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.835 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.356 ; 3.358 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.323 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.352 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.356 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.264 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.356 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #313: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.813 ; 85 ; 0.108 ; 0.930 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.283 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.310 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #314: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.267 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.360 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #315: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.333 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.359 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #316: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.908 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.271 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; -; 6.353 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #317: Setup slack is -0.760 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.389 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.760 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 2.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.996 ; 86 ; 0.421 ; 0.887 ; -; Cell ; ; 8 ; 0.188 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; 6.389 ; 2.317 ; ; ; ; ; ; data path ; -; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; -; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; -; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.363 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.389 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; -; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #318: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.344 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.346 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.875 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.344 ; 3.346 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.251 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.344 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.344 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.344 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #319: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.904 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.332 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.359 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #320: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.886 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.325 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.353 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #321: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.884 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.320 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.346 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #322: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.271 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.353 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #323: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.372 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.374 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.372 ; 3.374 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.285 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.372 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #324: Setup slack is -0.759 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.355 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.759 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.357 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.355 ; 3.357 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.328 ; 0.804 ; FF ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.355 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.355 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.355 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #325: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.700 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.278 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.306 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #326: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.701 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.279 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.307 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #327: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.359 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.361 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.904 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.359 ; 3.361 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.332 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.359 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #328: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.812 ; 85 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.283 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.312 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #329: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.265 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.358 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #330: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #331: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #332: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.348 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.350 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.348 ; 3.350 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.321 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.348 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #333: Setup slack is -0.758 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_csr_handler|decode_csr_address[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.498 ; -; Slack ; -0.758 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.141 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.872 ; 88 ; 0.666 ; 0.817 ; -; Cell ; ; 8 ; 0.267 ; 8 ; 0.000 ; 0.112 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.256 ; 3.264 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.868 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; -; 3.980 ; 0.112 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.986 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.663 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.690 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.694 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.406 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; -; 5.434 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; -; 5.439 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; -; 6.256 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|clk ; -; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; -; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.498 ; 0.177 ; ; uTsu ; 1 ; FF_X38_Y157_N17 ; ; vx_csr_handler|decode_csr_address[4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #334: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.276 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.304 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #335: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.278 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.306 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #336: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.277 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.305 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #337: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.351 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.353 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.905 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.351 ; 3.353 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.323 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.351 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #338: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.835 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.259 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.286 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.292 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.271 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.358 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #339: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #340: Setup slack is -0.757 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.757 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #341: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.275 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.303 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #342: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.934 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.312 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #343: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.899 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.311 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.310 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.337 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.341 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.302 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.329 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #344: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.337 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.339 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.879 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.337 ; 3.339 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.310 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.337 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #345: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.362 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.364 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.845 ; 85 ; 0.106 ; 1.302 ; -; Cell ; ; 12 ; 0.398 ; 12 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.362 ; 3.364 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.243 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.362 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.362 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.362 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #346: Setup slack is -0.756 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.756 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.710 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.478 ; 14 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.179 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; -; 6.307 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; -; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; -; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #347: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.357 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.359 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.839 ; 85 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.357 ; 3.359 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.986 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.016 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.022 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.282 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.357 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.357 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.357 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #348: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.356 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.358 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.356 ; 3.358 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.226 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.356 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #349: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.338 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.340 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.338 ; 3.340 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.310 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.338 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #350: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.315 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.341 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #351: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.899 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.311 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.310 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.337 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.341 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.302 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.329 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #352: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #353: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #354: Setup slack is -0.755 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.755 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #355: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.448 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.080 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.107 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.113 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.284 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.360 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #356: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.332 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.360 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #357: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.886 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.079 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.267 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.346 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #358: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.952 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.381 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.408 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.413 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.313 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.341 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #359: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.952 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.381 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.408 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.413 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.313 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; -; 6.341 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #360: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.680 ; 80 ; 0.192 ; 0.681 ; -; Cell ; ; 14 ; 0.554 ; 17 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.970 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.996 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.002 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.280 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.353 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #361: Setup slack is -0.754 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.754 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.261 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.353 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #362: Setup slack is -0.753 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.339 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.753 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.341 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.896 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.339 ; 3.341 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.313 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.339 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #363: Setup slack is -0.753 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.413 ; -; Slack ; -0.753 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.141 ; ; ; ; ; ; -; Data Delay ; 3.174 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.836 ; 89 ; 0.630 ; 0.817 ; -; Cell ; ; 8 ; 0.211 ; 7 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.166 ; 3.174 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.810 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; -; 3.890 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.896 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.573 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.600 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.604 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.316 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; -; 5.344 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; -; 5.349 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; -; 6.166 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; -; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #364: Setup slack is -0.753 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.753 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.695 ; 80 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.538 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.352 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.969 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.995 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 6.001 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.279 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.352 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.352 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.352 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #365: Setup slack is -0.753 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.365 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.753 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.367 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.907 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.365 ; 3.367 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.339 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.365 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #366: Setup slack is -0.753 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.552 ; -; Slack ; -0.753 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.710 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.476 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.179 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; -; 6.305 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #367: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.361 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.363 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.361 ; 3.363 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.122 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.151 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.157 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.285 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.361 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #368: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.360 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.362 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.448 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.360 ; 3.362 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.080 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.107 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.113 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.284 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.360 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #369: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.358 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.360 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.912 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.358 ; 3.360 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.330 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.358 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #370: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.937 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.319 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.345 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #371: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.222 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.224 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.827 ; 88 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.222 ; 3.224 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.222 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #372: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.351 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.359 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.706 ; 81 ; 0.142 ; 0.710 ; -; Cell ; ; 14 ; 0.528 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.351 ; 3.359 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.962 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.990 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.996 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.276 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.351 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #373: Setup slack is -0.752 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.353 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.752 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.355 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.353 ; 3.355 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.261 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.353 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #374: Setup slack is -0.751 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.361 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.751 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.363 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.361 ; 3.363 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.112 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.139 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.145 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.283 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.361 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #375: Setup slack is -0.751 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.751 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.817 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.243 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.336 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #376: Setup slack is -0.751 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.751 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.937 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.319 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.345 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #377: Setup slack is -0.751 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[1] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.751 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.079 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.678 ; 81 ; 0.127 ; 0.747 ; -; Cell ; ; 16 ; 0.447 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 6.252 ; 3.308 ; ; ; ; ; ; data path ; -; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; -; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; -; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; -; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; -; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; -; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; -; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; -; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; -; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.444 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.472 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.477 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.224 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #378: Setup slack is -0.750 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.750 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.696 ; 81 ; 0.192 ; 0.712 ; -; Cell ; ; 14 ; 0.520 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.274 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.336 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #379: Setup slack is -0.750 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.750 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.840 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.319 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.346 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #380: Setup slack is -0.749 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.749 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.273 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.335 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #381: Setup slack is -0.749 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.749 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.266 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.349 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #382: Setup slack is -0.749 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.348 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.749 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.350 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.886 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.348 ; 3.350 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.322 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.348 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #383: Setup slack is -0.749 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.749 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.867 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.079 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.262 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.341 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #384: Setup slack is -0.748 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.748 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.876 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.304 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.332 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #385: Setup slack is -0.748 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.350 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.748 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.352 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.674 ; 80 ; 0.192 ; 0.690 ; -; Cell ; ; 14 ; 0.557 ; 17 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.350 ; 3.352 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.979 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.008 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.014 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.277 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.350 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #386: Setup slack is -0.748 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.377 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.748 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.098 ; ; ; ; ; ; -; Data Delay ; 2.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.939 ; 84 ; 0.403 ; 0.872 ; -; Cell ; ; 8 ; 0.241 ; 10 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; -; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; 6.377 ; 2.320 ; ; ; ; ; ; data path ; -; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; -; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; -; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; -; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.915 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; -; 6.318 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; -; 6.377 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; -; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; -; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #387: Setup slack is -0.748 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.748 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.302 ; 0.809 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.329 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #388: Setup slack is -0.747 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.347 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.747 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.347 ; 3.349 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.254 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.347 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.347 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.347 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #389: Setup slack is -0.747 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.747 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.918 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.314 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.340 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #390: Setup slack is -0.747 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.747 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.357 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.689 ; 80 ; 0.192 ; 0.690 ; -; Cell ; ; 14 ; 0.541 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.349 ; 3.357 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.978 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.007 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.013 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.276 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.349 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #391: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.306 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.334 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #392: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.306 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.334 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #393: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.864 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.302 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.329 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #394: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.876 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.312 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #395: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.925 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.307 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.333 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #396: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.918 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.314 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.340 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #397: Setup slack is -0.746 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.350 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.746 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.352 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.350 ; 3.352 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.377 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.407 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.411 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.264 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.350 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #398: Setup slack is -0.745 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.745 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.697 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.477 ; 14 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.166 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; -; 6.293 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #399: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 84 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.265 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.293 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #400: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 84 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.264 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.292 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #401: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.327 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.327 ; 3.329 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.300 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.327 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #402: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.811 ; 85 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.270 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.299 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #403: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.810 ; 85 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.269 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.299 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #404: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.876 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.351 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.246 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.273 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.279 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.258 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.345 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #405: Setup slack is -0.744 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.350 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.744 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.352 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.873 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.350 ; 3.352 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.323 ; 0.800 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.350 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #406: Setup slack is -0.743 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.743 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 83 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.223 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.330 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #407: Setup slack is -0.743 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.743 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.779 ; 84 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.262 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.290 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #408: Setup slack is -0.743 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.743 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.929 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.309 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.336 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #409: Setup slack is -0.743 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.743 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.851 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.365 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.256 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.335 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #410: Setup slack is -0.743 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.338 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.743 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.340 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.338 ; 3.340 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.275 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.355 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.359 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.213 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; -; 6.338 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; -; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; -; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #411: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 83 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.223 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.329 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #412: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.867 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.302 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.328 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #413: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.807 ; 85 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.266 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.296 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #414: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.207 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.752 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.207 ; 3.209 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.207 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #415: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.207 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.752 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.207 ; 3.209 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.207 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #416: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.908 ; 87 ; 0.106 ; 1.378 ; -; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.306 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.336 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #417: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.295 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.323 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #418: Setup slack is -0.742 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.347 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.742 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.347 ; 3.349 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.320 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.347 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #419: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.258 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #420: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.347 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.349 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.347 ; 3.349 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.319 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.347 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #421: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.902 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.308 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.334 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #422: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.342 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.344 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.840 ; 85 ; 0.096 ; 1.046 ; -; Cell ; ; 14 ; 0.382 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.342 ; 3.344 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.493 ; 0.096 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.569 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.574 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.620 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.646 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.650 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.775 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.799 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.805 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.209 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.235 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.241 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.255 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.342 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #423: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.055 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.418 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.275 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.355 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.359 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.213 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; -; 6.336 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; -; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #424: Setup slack is -0.741 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.741 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.906 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.302 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.328 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #425: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.902 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.308 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.334 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #426: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.342 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.350 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.675 ; 80 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.550 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.342 ; 3.350 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.971 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 6.000 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 6.006 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.269 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.342 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #427: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.552 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.309 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.336 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #428: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.258 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.345 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #429: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.808 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.276 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; -; 6.304 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #430: Setup slack is -0.740 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.740 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.807 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.275 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; -; 6.304 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #431: Setup slack is -0.739 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.154 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.739 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.156 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.696 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.154 ; 3.156 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.154 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #432: Setup slack is -0.739 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.739 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.838 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.536 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.291 ; 0.755 ; FF ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.318 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #433: Setup slack is -0.739 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.739 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.125 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.715 ; 84 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.410 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.171 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; -; 6.244 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #434: Setup slack is -0.739 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.739 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.908 ; 87 ; 0.106 ; 1.378 ; -; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.306 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.336 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #435: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[2] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.354 ; -; Data Required Time ; 5.616 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.365 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.842 ; 84 ; 0.122 ; 0.777 ; -; Cell ; ; 16 ; 0.403 ; 12 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; -; 6.354 ; 3.365 ; ; ; ; ; ; data path ; -; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; -; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; -; 3.952 ; 0.777 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|datae ; -; 4.029 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; -; 4.034 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; -; 4.461 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; -; 4.487 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.492 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.847 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.875 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.881 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.144 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.203 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.209 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.332 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.395 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.399 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.174 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.201 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.206 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.328 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.354 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.354 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.354 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #436: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.195 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.195 ; 3.197 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #437: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.337 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.345 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.568 ; 77 ; 0.118 ; 0.708 ; -; Cell ; ; 14 ; 0.651 ; 19 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.337 ; 3.345 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.948 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.976 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.982 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.262 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.337 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.337 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.337 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #438: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.264 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.292 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #439: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.352 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.354 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.352 ; 3.354 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.326 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.352 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #440: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.154 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.156 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.696 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.154 ; 3.156 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.154 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #441: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.336 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #442: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.884 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.313 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.341 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #443: Setup slack is -0.738 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.503 ; -; Slack ; -0.738 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.622 ; 80 ; 0.125 ; 0.816 ; -; Cell ; ; 14 ; 0.548 ; 17 ; 0.000 ; 0.124 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; 6.241 ; 3.293 ; ; ; ; ; ; data path ; -; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; -; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; -; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; -; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; -; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; -; 4.457 ; 0.493 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30|datad ; -; 4.539 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 6 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30~la_lab/laboutb[16] ; -; 4.722 ; 0.179 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36|datac ; -; 4.815 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36|combout ; -; 4.821 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36~la_mlab/laboutb[3] ; -; 4.946 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|dataa ; -; 5.070 ; 0.124 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; -; 5.076 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; -; 5.301 ; 0.225 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; -; 5.379 ; 0.078 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; -; 5.385 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; -; 6.169 ; 0.784 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; -; 6.241 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #444: Setup slack is -0.737 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.737 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.264 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.292 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #445: Setup slack is -0.737 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.737 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 83 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.202 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.336 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #446: Setup slack is -0.737 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.737 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.228 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.321 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #447: Setup slack is -0.737 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.737 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.802 ; 85 ; 0.108 ; 0.935 ; -; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.260 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.288 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #448: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.342 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.344 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.342 ; 3.344 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.062 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.089 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.095 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.266 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.342 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #449: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 84 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.426 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.260 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.322 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #450: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.791 ; 85 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.262 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.290 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #451: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.411 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.299 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.328 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.332 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.240 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.332 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #452: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.350 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.352 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.906 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.350 ; 3.352 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.324 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.350 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #453: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.927 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.309 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.335 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #454: Setup slack is -0.736 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.344 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.736 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.346 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 83 ; 0.107 ; 0.868 ; -; Cell ; ; 14 ; 0.460 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.344 ; 3.346 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.127 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; -; 6.155 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; -; 6.161 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; -; 6.268 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; -; 6.344 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; -; 6.344 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; -; 6.344 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #455: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.678 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.256 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.283 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #456: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.195 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.195 ; 3.197 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #457: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.871 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.301 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.328 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #458: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.788 ; 85 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.380 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.259 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.288 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #459: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.870 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.308 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.335 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #460: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.435 ; 13 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.200 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.334 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #461: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.319 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.319 ; 3.321 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.226 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.319 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #462: Setup slack is -0.735 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.735 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.890 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.296 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.322 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #463: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.342 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.344 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.342 ; 3.344 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.062 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.089 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.095 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.266 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.342 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #464: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.255 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.282 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #465: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.195 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.195 ; 3.197 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #466: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.341 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.733 ; 82 ; 0.128 ; 0.722 ; -; Cell ; ; 14 ; 0.483 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.333 ; 3.341 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.944 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.972 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.978 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.258 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.333 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #467: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.870 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.308 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.335 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #468: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.297 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.326 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.330 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.238 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.330 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #469: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.504 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.510 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.241 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.334 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #470: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.847 ; 88 ; 0.590 ; 0.986 ; -; Cell ; ; 10 ; 0.273 ; 8 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.239 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.798 ; 0.635 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; -; 3.879 ; 0.081 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.885 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.521 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.548 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.552 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.538 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; -; 5.565 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; -; 5.570 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; -; 6.160 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; -; 6.239 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #471: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.902 ; 87 ; 0.106 ; 1.372 ; -; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.300 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.330 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #472: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.419 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.214 ; 0.297 ; RR ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.245 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.243 ; 0.998 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.333 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #473: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.830 ; 84 ; 0.106 ; 1.300 ; -; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.349 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #474: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.333 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #475: Setup slack is -0.734 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.349 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.734 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.351 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.830 ; 84 ; 0.106 ; 1.300 ; -; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.349 ; 3.351 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.349 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #476: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[2] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.357 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.834 ; 84 ; 0.114 ; 0.777 ; -; Cell ; ; 16 ; 0.403 ; 12 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; -; 6.346 ; 3.357 ; ; ; ; ; ; data path ; -; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; -; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; -; 3.952 ; 0.777 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|datae ; -; 4.029 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; -; 4.034 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; -; 4.461 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; -; 4.487 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.492 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.847 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.875 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.881 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.144 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.203 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.209 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.332 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.395 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.399 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.174 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.201 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.206 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.320 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.346 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #477: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.306 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.333 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #478: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.316 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.854 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.316 ; 3.318 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.289 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.316 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #479: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.327 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.917 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.327 ; 3.329 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.299 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.327 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #480: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.374 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.235 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.268 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.247 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.334 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #481: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.320 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.322 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.930 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.320 ; 3.322 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.293 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.320 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #482: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.844 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.294 ; 0.940 ; FF ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; -; 6.323 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #483: Setup slack is -0.733 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.733 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.307 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.334 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #484: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.288 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.315 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #485: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.306 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.333 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #486: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.797 ; 85 ; 0.108 ; 0.930 ; -; Cell ; ; 12 ; 0.366 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.255 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.282 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #487: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.320 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.322 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.930 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.320 ; 3.322 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.293 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; -; 6.320 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #488: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.296 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.323 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #489: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.563 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.287 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.314 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #490: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.414 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.254 ; 0.328 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.280 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.285 ; 0.005 ; FF ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.244 ; 0.959 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.328 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #491: Setup slack is -0.732 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.336 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.732 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.336 ; 3.338 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.336 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #492: Setup slack is -0.731 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.731 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.847 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.276 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.303 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #493: Setup slack is -0.731 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.731 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.286 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.314 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #494: Setup slack is -0.731 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.731 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 83 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.202 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.332 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #495: Setup slack is -0.731 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.731 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.908 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.304 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.330 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #496: Setup slack is -0.731 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.731 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.830 ; 85 ; 0.106 ; 1.300 ; -; Cell ; ; 12 ; 0.397 ; 12 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.346 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #497: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.922 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.301 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.329 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #498: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.796 ; 85 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.255 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.284 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #499: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.868 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.301 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.328 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #500: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.324 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.326 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.865 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.324 ; 3.326 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.297 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.324 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #501: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.243 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.330 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #502: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.341 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.343 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.880 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.341 ; 3.343 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.313 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.341 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #503: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.324 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.326 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.414 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.324 ; 3.326 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.254 ; 0.328 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.280 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.285 ; 0.005 ; FF ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.240 ; 0.955 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.324 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #504: Setup slack is -0.730 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.730 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.880 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.312 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #505: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.665 ; 81 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.278 ; 3.286 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.250 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.278 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #506: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 81 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.277 ; 3.285 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.249 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.277 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #507: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.902 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.280 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.307 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #508: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.320 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.322 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.914 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.320 ; 3.322 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.293 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.320 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #509: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.868 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.284 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.312 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #510: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.200 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.330 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #511: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.908 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.289 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.315 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #512: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.473 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.499 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.505 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.236 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.329 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.329 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.329 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #513: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.866 ; 86 ; 0.127 ; 1.302 ; -; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.211 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.328 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.328 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.328 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #514: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.328 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.330 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.869 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.328 ; 3.330 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.300 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.328 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #515: Setup slack is -0.729 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.729 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.333 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #516: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.662 ; 81 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.275 ; 3.283 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.247 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.275 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #517: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.705 ; 82 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.277 ; 3.285 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.249 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.277 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #518: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.704 ; 82 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.276 ; 3.284 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.248 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.276 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #519: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.336 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.924 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.334 ; 3.336 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.306 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.334 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #520: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.898 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.294 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.322 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #521: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.845 ; 87 ; 0.119 ; 0.922 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.251 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #522: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.345 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.347 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.885 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.345 ; 3.347 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.317 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.345 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #523: Setup slack is -0.728 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.346 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.728 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.348 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.821 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.346 ; 3.348 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.253 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.346 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #524: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.342 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.873 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.340 ; 3.342 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.253 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.340 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.340 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.340 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #525: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.862 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.239 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.321 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #526: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.702 ; 82 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.274 ; 3.282 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.246 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.274 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #527: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.219 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.312 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #528: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.896 ; 87 ; 0.106 ; 1.366 ; -; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.294 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.322 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #529: Setup slack is -0.727 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.325 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.727 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.327 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.869 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.325 ; 3.327 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.299 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.325 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #530: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.052 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.079 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.085 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.256 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.332 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #531: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.316 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.316 ; 3.318 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.289 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.316 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #532: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.812 ; 86 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.252 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.281 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #533: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.811 ; 86 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.251 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.281 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #534: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.325 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.333 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.726 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.482 ; 14 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.325 ; 3.333 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.936 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.964 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.970 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.250 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.325 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #535: Setup slack is -0.726 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.726 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.240 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.332 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #536: Setup slack is -0.725 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.725 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.802 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.217 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.310 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #537: Setup slack is -0.725 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.339 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.725 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.341 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.339 ; 3.341 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.313 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.339 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #538: Setup slack is -0.725 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.324 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.725 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.326 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.892 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.324 ; 3.326 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.298 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.324 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #539: Setup slack is -0.725 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.725 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.284 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.312 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #540: Setup slack is -0.725 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.725 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.284 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.312 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #541: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.764 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.450 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.094 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.123 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.129 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.257 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.333 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #542: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.052 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.079 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.085 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.256 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.332 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #543: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.900 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.278 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.305 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #544: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.280 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.307 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #545: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.326 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.328 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.923 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.283 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.326 ; 3.328 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.300 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.326 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #546: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.280 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.308 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #547: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 83 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.453 ; 14 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.189 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.323 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #548: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.215 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.308 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #549: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.284 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.310 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #550: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.808 ; 86 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.248 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.278 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #551: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.269 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.278 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.305 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.309 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.270 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.297 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #552: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_f_d_reg|curr_PC[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.194 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.192 ; 3.194 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.192 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #553: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_f_d_reg|curr_PC[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.194 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.192 ; 3.194 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.192 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #554: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.330 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.332 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.866 ; 86 ; 0.127 ; 1.302 ; -; Cell ; ; 12 ; 0.344 ; 10 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.330 ; 3.332 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.211 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.330 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #555: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.311 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.313 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.604 ; 79 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.588 ; 18 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.311 ; 3.313 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.204 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.311 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #556: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.455 ; 0.538 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.530 ; 0.075 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.534 ; 0.004 ; FF ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.295 ; 0.761 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; -; 6.322 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #557: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.338 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.340 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.821 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.338 ; 3.340 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.252 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.338 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #558: Setup slack is -0.724 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.724 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.231 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.313 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #559: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.764 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.450 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.084 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.111 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.117 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.255 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.333 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #560: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.325 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.333 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.554 ; 77 ; 0.118 ; 0.714 ; -; Cell ; ; 14 ; 0.653 ; 20 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.325 ; 3.333 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.954 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.984 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.990 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.250 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.325 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #561: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.268 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.295 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #562: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.544 ; 77 ; 0.118 ; 0.688 ; -; Cell ; ; 14 ; 0.648 ; 20 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.310 ; 3.318 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.236 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.310 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #563: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.319 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.319 ; 3.321 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.286 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.315 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.319 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.227 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.319 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #564: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.329 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.331 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.905 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.329 ; 3.331 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.301 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.329 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #565: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 87 ; 0.119 ; 0.916 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.245 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #566: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.378 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.467 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.493 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.499 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.230 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.323 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #567: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.574 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.269 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.278 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.305 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.309 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.270 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; -; 6.297 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #568: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.604 ; 79 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.587 ; 18 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.204 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.310 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #569: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.619 ; 79 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.572 ; 17 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.310 ; 3.318 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.203 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.310 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #570: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.847 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.279 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.306 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #571: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.169 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.698 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.167 ; 3.169 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.167 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|sclr ; -; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N40 ; ; vx_d_e_reg|a_reg_data[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #572: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.862 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.296 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.322 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #573: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|a_reg_data[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.169 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.698 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.167 ; 3.169 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.167 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|sclr ; -; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #574: Setup slack is -0.723 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.723 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.231 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.313 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #575: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.851 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.229 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.321 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #576: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.911 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.290 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.318 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #577: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.864 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.293 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.321 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #578: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.278 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.306 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #579: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.860 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.295 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.322 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #580: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.316 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.882 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.315 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.316 ; 3.318 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.288 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.316 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #581: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #582: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #583: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #584: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.619 ; 79 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.571 ; 17 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.309 ; 3.317 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.203 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.309 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #585: Setup slack is -0.722 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.335 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.722 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.337 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.335 ; 3.337 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.243 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.335 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #586: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.660 ; 80 ; 0.116 ; 0.712 ; -; Cell ; ; 14 ; 0.530 ; 16 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.307 ; 3.315 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.245 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.307 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #587: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.242 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.269 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #588: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.333 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.335 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.928 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.333 ; 3.335 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.307 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.333 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #589: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.285 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.312 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #590: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.844 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.272 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.299 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #591: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.860 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.295 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.322 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #592: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.697 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.319 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.136 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #593: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.320 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.322 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.808 ; 85 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.320 ; 3.322 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.203 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.320 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.320 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.320 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #594: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.395 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.424 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.428 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.272 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.298 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #595: Setup slack is -0.721 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|rs1[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.721 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.789 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.257 ; 0.843 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|dataf ; -; 6.285 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|combout ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|d ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N2 ; ; vx_d_e_reg|rs1[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #596: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.280 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.308 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #597: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.280 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.308 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #598: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 85 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.241 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.269 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #599: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 85 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.240 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.268 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #600: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.851 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.229 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.321 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #601: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.700 ; 81 ; 0.117 ; 0.712 ; -; Cell ; ; 14 ; 0.489 ; 15 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.306 ; 3.314 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.244 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.306 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #602: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.895 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.276 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.303 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #603: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.697 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.319 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.136 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #604: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.190 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.192 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.735 ; 86 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.190 ; 3.192 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.425 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.759 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.787 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.792 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.190 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #605: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.788 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.256 ; 0.842 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|dataf ; -; 6.284 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N7 ; ; vx_d_e_reg|csr_mask[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #606: Setup slack is -0.720 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.720 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.122 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.364 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.205 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|dataf ; -; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; -; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N22 ; ; vx_d_e_reg|csr_address[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #607: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 85 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.238 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.266 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #608: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.719 ; 82 ; 0.128 ; 0.722 ; -; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.321 ; 3.329 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.950 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.980 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.986 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.246 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.321 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #609: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.332 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.334 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.332 ; 3.334 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.245 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.332 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #610: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.231 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.313 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #611: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.803 ; 86 ; 0.108 ; 0.935 ; -; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.242 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.270 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #612: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #613: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #614: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.291 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.318 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #615: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.220 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.087 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.566 ; 79 ; 0.120 ; 0.864 ; -; Cell ; ; 16 ; 0.520 ; 16 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 6.220 ; 3.268 ; ; ; ; ; ; data path ; -; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; -; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; -; 4.042 ; 0.864 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|dataf ; -; 4.069 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|combout ; -; 4.075 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22~la_mlab/laboutb[3] ; -; 4.196 ; 0.121 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datab ; -; 4.307 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; -; 4.313 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; -; 4.437 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; -; 4.527 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; -; 4.533 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; -; 4.653 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; -; 4.785 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.789 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.222 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.255 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.412 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.440 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.445 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.192 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.220 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #616: Setup slack is -0.719 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[29] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.419 ; -; Slack ; -0.719 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.419 ; 0.014 ; ; uTsu ; 1 ; FF_X80_Y155_N22 ; ; vx_d_e_reg|PC_next_out[29] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #617: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.287 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.314 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #618: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.281 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.308 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #619: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.839 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.273 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.301 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #620: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.319 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 83 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.319 ; 3.321 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.189 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.319 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #621: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.873 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.278 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.304 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #622: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[27] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.420 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.420 ; 0.015 ; ; uTsu ; 1 ; FF_X80_Y155_N16 ; ; vx_d_e_reg|PC_next_out[27] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #623: Setup slack is -0.718 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[9] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.718 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.595 ; 79 ; 0.131 ; 0.774 ; -; Cell ; ; 16 ; 0.443 ; 14 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 6.219 ; 3.272 ; ; ; ; ; ; data path ; -; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; -; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; -; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; -; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; -; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; -; 4.234 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|datad ; -; 4.323 ; 0.089 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|combout ; -; 4.329 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32~la_mlab/laboutt[1] ; -; 4.460 ; 0.131 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataf ; -; 4.488 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.492 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.709 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.784 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.788 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.221 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.411 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.439 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.444 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.191 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.219 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #624: Setup slack is -0.717 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.317 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.717 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.319 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.317 ; 3.319 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.234 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #625: Setup slack is -0.717 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.323 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.717 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.315 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.323 ; 3.325 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.295 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.323 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #626: Setup slack is -0.717 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.421 ; -; Slack ; -0.717 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.421 ; 0.016 ; ; uTsu ; 1 ; FF_X80_Y155_N14 ; ; vx_d_e_reg|PC_next_out[26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #627: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.270 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.297 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #628: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.865 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.292 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.318 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #629: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.854 ; 87 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.299 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.241 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.271 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #630: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.855 ; 87 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.242 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.271 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #631: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.157 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.159 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.157 ; 3.159 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; -; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #632: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.157 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.159 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.157 ; 3.159 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; -; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #633: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.157 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.159 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.157 ; 3.159 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; -; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #634: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.181 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.183 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.181 ; 3.183 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.181 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.181 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #635: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.181 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.183 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.181 ; 3.183 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.181 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.181 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #636: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.324 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.808 ; 84 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.394 ; 12 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.322 ; 3.324 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.203 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.322 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #637: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.605 ; 79 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.581 ; 18 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.303 ; 3.311 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.196 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.303 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #638: Setup slack is -0.716 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.716 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; -; 6.293 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #639: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.771 ; 85 ; 0.108 ; 0.888 ; -; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.242 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; -; 6.269 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #640: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.232 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.315 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.315 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #641: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.876 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.271 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.298 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #642: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.157 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.159 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.157 ; 3.159 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; -; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #643: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.605 ; 79 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.580 ; 18 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.302 ; 3.310 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.196 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.302 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #644: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.319 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.860 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.319 ; 3.321 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.366 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; -; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; -; 5.399 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; -; 6.292 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; -; 6.319 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; -; 6.319 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; -; 6.319 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #645: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.261 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; -; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #646: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_address[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.122 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.743 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.365 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.227 ; 3.229 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.199 ; 0.780 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|dataf ; -; 6.227 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|combout ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|d ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; -; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N11 ; ; vx_d_e_reg|csr_address[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #647: Setup slack is -0.715 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.715 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.884 ; 87 ; 0.106 ; 1.354 ; -; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.282 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.310 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #648: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.345 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.375 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.379 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.232 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.318 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #649: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.221 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.313 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #650: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.282 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.310 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #651: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.773 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.206 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.299 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #652: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.798 ; 86 ; 0.108 ; 0.930 ; -; Cell ; ; 12 ; 0.346 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.237 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.264 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #653: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.851 ; 87 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.299 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.238 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.268 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #654: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[1] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.013 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.675 ; 80 ; 0.122 ; 0.777 ; -; Cell ; ; 16 ; 0.534 ; 16 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.129 ; 4 ; 0.129 ; 0.129 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]|clk ; -; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1] ; -; 6.313 ; 3.338 ; ; ; ; ; ; data path ; -; 3.104 ; 0.129 ; RR ; uTco ; 1 ; FF_X40_Y149_N38 ; ; vx_csr_handler|decode_csr_address[1]|q ; -; 3.167 ; 0.063 ; RR ; CELL ; 548 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]~la_lab/laboutb[5] ; -; 3.808 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|datae ; -; 3.883 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; -; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; -; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; -; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; -; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; -; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; -; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; -; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; -; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; -; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.287 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.313 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #655: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.013 ; ; ; ; ; ; -; Data Delay ; 3.338 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.743 ; 82 ; 0.122 ; 0.777 ; -; Cell ; ; 16 ; 0.469 ; 14 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|clk ; -; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; -; 6.313 ; 3.338 ; ; ; ; ; ; data path ; -; 3.101 ; 0.126 ; FF ; uTco ; 1 ; FF_X40_Y149_N28 ; ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|q ; -; 3.145 ; 0.044 ; FF ; CELL ; 363 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE~la_lab/laboutt[18] ; -; 3.854 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|dataf ; -; 3.883 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; -; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; -; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; -; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; -; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; -; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; -; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; -; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; -; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; -; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.287 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.313 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #656: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.824 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.524 ; 0.005 ; FF ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.273 ; 0.749 ; FF ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; -; 6.301 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #657: Setup slack is -0.714 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.714 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.320 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.415 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.318 ; 3.320 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.233 ; 0.740 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; -; 6.318 ; 0.085 ; FF ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #658: Setup slack is -0.713 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.713 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.273 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.301 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #659: Setup slack is -0.713 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.713 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.273 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.301 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #660: Setup slack is -0.713 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.325 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.713 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.327 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.870 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.325 ; 3.327 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.299 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.325 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #661: Setup slack is -0.713 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.713 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.884 ; 87 ; 0.106 ; 1.354 ; -; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.282 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.310 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #662: Setup slack is -0.713 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.425 ; -; Slack ; -0.713 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.425 ; 0.020 ; ; uTsu ; 1 ; FF_X80_Y155_N25 ; ; vx_d_e_reg|PC_next_out[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #663: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.766 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.413 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.192 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.299 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #664: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 84 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.236 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.298 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #665: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.221 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.313 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #666: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.311 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.319 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.677 ; 81 ; 0.136 ; 0.708 ; -; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.311 ; 3.319 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.214 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.922 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.950 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.956 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.236 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.311 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.311 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.311 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #667: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.566 ; 78 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.261 ; 3.269 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.233 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.261 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #668: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.565 ; 78 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.260 ; 3.268 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.232 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #669: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.326 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.328 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.918 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.326 ; 3.328 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.300 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.326 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #670: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.797 ; 86 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.237 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.266 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #671: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N1 ; ; vx_d_e_reg|PC_next_out[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #672: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[23] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N5 ; ; vx_d_e_reg|PC_next_out[23] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #673: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N7 ; ; vx_d_e_reg|PC_next_out[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #674: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N19 ; ; vx_d_e_reg|PC_next_out[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #675: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.835 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.547 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.266 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; -; 6.293 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #676: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N29 ; ; vx_d_e_reg|PC_next_out[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #677: Setup slack is -0.712 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.712 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.881 ; 87 ; 0.106 ; 1.351 ; -; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.279 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; -; 6.307 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #678: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.659 ; 80 ; 0.192 ; 0.681 ; -; Cell ; ; 14 ; 0.531 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.927 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.953 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.959 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.237 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.310 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #679: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.766 ; 84 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.412 ; 12 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.192 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.298 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #680: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 1.046 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.450 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.479 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.484 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.226 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.306 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #681: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.277 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.304 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #682: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.267 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.295 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #683: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.563 ; 78 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.258 ; 3.266 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.230 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.258 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #684: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.176 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.310 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #685: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.823 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.202 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.295 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #686: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.862 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.567 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.224 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; -; 6.303 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #687: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.126 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.128 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.740 ; 88 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.268 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.126 ; 3.128 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.126 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.126 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #688: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.484 ; 15 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.313 ; 3.321 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.942 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.972 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.978 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.238 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.313 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #689: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.702 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.479 ; 14 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.298 ; 3.306 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.504 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.530 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.536 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.224 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.298 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #690: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.536 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.267 ; 0.731 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; -; 6.293 ; 0.026 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #691: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.138 ; -; Data Required Time ; 5.427 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.140 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.138 ; 3.140 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|sclr ; -; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.427 ; 0.022 ; ; uTsu ; 1 ; FF_X80_Y155_N11 ; ; vx_d_e_reg|PC_next_out[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #692: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.285 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; -; 6.312 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #693: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.311 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.313 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.851 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.311 ; 3.313 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.284 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; -; 6.311 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; -; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; -; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #694: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.536 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.696 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.432 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.165 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; -; 6.247 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.536 ; 0.150 ; ; uTsu ; 1 ; FF_X79_Y151_N58 ; ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #695: Setup slack is -0.711 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.711 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.775 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.270 ; 0.799 ; FF ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; -; 6.297 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #696: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.750 ; 83 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.926 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.952 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.958 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.236 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.309 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #697: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.169 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.167 ; 3.169 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #698: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.405 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.485 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.490 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.263 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.291 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #699: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.288 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.315 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #700: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.383 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.279 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.306 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #701: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.777 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.236 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.264 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #702: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.273 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.302 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.306 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.214 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.306 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #703: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.126 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.128 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.740 ; 88 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.268 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.126 ; 3.128 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.126 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.126 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #704: Setup slack is -0.710 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.710 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.929 ; 89 ; 0.114 ; 1.378 ; -; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.274 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.304 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #705: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.304 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.302 ; 3.304 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.442 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.473 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.275 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.302 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #706: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.777 ; 85 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.236 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.264 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #707: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.282 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.309 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #708: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.860 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.265 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.292 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #709: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.304 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.302 ; 3.304 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.276 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #710: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.174 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.176 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.174 ; 3.176 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.174 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.174 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #711: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.174 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.176 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.174 ; 3.176 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.174 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.174 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #712: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.179 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.181 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.625 ; 83 ; 0.163 ; 1.398 ; -; Cell ; ; 10 ; 0.435 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.179 ; 3.181 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 4.696 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; -; 4.776 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.781 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.179 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.179 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #713: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.300 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.302 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.300 ; 3.302 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.273 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; -; 6.300 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #714: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.300 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.302 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.840 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.300 ; 3.302 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.272 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; -; 6.300 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #715: Setup slack is -0.709 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.709 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.524 ; 0.005 ; FF ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.281 ; 0.757 ; FF ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; -; 6.308 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #716: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.850 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.277 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.304 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #717: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.775 ; 85 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.234 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.262 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #718: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.282 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.309 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #719: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.304 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.913 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.302 ; 3.304 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.276 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; -; 6.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #720: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.178 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.020 ; ; ; ; ; ; -; Data Delay ; 3.186 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.640 ; 83 ; 0.163 ; 1.398 ; -; Cell ; ; 10 ; 0.419 ; 13 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.178 ; 3.186 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 4.695 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; -; 4.775 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.780 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.178 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.178 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #721: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.276 ; 0.878 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.306 ; 0.030 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #722: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.319 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.321 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.760 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.319 ; 3.321 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.239 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; -; 6.319 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; -; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #723: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.836 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.269 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; -; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #724: Setup slack is -0.708 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.708 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.716 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.424 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.185 ; 0.770 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|datae ; -; 6.259 ; 0.074 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #725: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.169 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.167 ; 3.169 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #726: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.772 ; 85 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.231 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.260 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #727: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.899 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.295 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.321 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #728: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.177 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.179 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.725 ; 86 ; 0.110 ; 1.398 ; -; Cell ; ; 10 ; 0.333 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.177 ; 3.179 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.412 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.746 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.774 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.779 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.177 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #729: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.929 ; 89 ; 0.114 ; 1.378 ; -; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.274 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.304 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #730: Setup slack is -0.707 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.707 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.823 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.274 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; -; 6.301 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #731: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.642 ; 81 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.254 ; 3.262 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.227 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.254 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #732: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.316 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.318 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.818 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.380 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.316 ; 3.318 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.077 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.103 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.109 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.256 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.316 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #733: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.430 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.076 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.105 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.111 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.239 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.315 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #734: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.169 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.167 ; 3.169 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #735: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.905 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.281 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.309 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #736: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.312 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.314 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.907 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.312 ; 3.314 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.285 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.312 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #737: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.337 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.367 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.371 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.224 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.310 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #738: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.121 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.692 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.406 ; 13 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.145 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; -; 6.218 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #739: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[3] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.322 ; -; Data Required Time ; 5.616 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.333 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.860 ; 86 ; 0.122 ; 0.795 ; -; Cell ; ; 16 ; 0.352 ; 11 ; 0.000 ; 0.063 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; -; 6.322 ; 3.333 ; ; ; ; ; ; data path ; -; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; -; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; -; 3.968 ; 0.795 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|dataf ; -; 3.997 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; -; 4.002 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; -; 4.429 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; -; 4.455 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.815 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.843 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.849 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.112 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.171 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.177 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.300 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.363 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.367 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.142 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.169 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.174 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.296 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.322 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #740: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.773 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.412 ; 12 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.451 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.171 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.305 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #741: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.366 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.197 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.290 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #742: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; -; Cell ; ; 12 ; 0.345 ; 10 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.304 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #743: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.321 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.323 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.321 ; 3.323 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.455 ; 0.538 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.530 ; 0.075 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.534 ; 0.004 ; FF ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.294 ; 0.760 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; -; 6.321 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #744: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.340 ; -; Data Required Time ; 5.634 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.093 ; ; ; ; ; ; -; Data Delay ; 2.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.897 ; 83 ; 0.361 ; 0.872 ; -; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; -; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; 6.340 ; 2.283 ; ; ; ; ; ; data path ; -; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; -; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; -; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; -; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.916 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; -; 6.277 ; 0.361 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|datae ; -; 6.340 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|combout ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|d ; -; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y157_N37 ; ; vx_fetch|VX_Warp_one|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #745: Setup slack is -0.706 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.339 ; -; Data Required Time ; 5.633 ; -; Slack ; -0.706 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.093 ; ; ; ; ; ; -; Data Delay ; 2.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.896 ; 83 ; 0.360 ; 0.872 ; -; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; -; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; -; 6.339 ; 2.282 ; ; ; ; ; ; data path ; -; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; -; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; -; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; -; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.916 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; -; 6.276 ; 0.360 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|datae ; -; 6.339 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|combout ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|d ; -; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N43 ; ; vx_fetch|VX_Warp_two|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #746: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.653 ; 80 ; 0.192 ; 0.690 ; -; Cell ; ; 14 ; 0.534 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.936 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.965 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.971 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.234 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.307 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #747: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.430 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.066 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.093 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.099 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.237 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.315 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #748: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.682 ; 82 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.454 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.253 ; 3.261 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.226 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.253 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #749: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.650 ; 81 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.254 ; 3.262 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.226 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.254 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #750: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.649 ; 81 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.253 ; 3.261 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.225 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.253 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #751: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.880 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.509 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.260 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.288 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #752: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.176 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.306 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #753: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.368 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.268 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.297 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.301 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.209 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.301 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #754: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.786 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.480 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; -; 6.266 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; -; 6.293 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #755: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.160 ; -; Data Required Time ; 5.455 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.162 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.160 ; 3.162 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|sload ; -; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N26 ; ; vx_fetch|VX_Warp_zero|real_PC[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #756: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.160 ; -; Data Required Time ; 5.455 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.162 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.160 ; 3.162 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|sload ; -; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #757: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.024 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.166 ; 3.168 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|sload ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; -; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #758: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[0] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.300 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.110 ; ; ; ; ; ; -; Data Delay ; 2.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 1.828 ; 82 ; 0.876 ; 0.952 ; -; Cell ; ; 6 ; 0.215 ; 10 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; 6.300 ; 2.227 ; ; ; ; ; ; data path ; -; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; -; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; -; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; -; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; -; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; -; 6.214 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N27 ; High Speed ; vx_fetch|VX_Warp_one|i199~0|datae ; -; 6.300 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N27 ; High Speed ; vx_fetch|VX_Warp_one|i199~0|combout ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0]|d ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0] ; -; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.162 ; ; uTsu ; 1 ; FF_X69_Y156_N28 ; ; vx_fetch|VX_Warp_one|real_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #759: Setup slack is -0.705 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.705 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.213 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.305 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #760: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.744 ; 83 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.442 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.935 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.964 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.970 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.233 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.306 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #761: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.759 ; 85 ; 0.108 ; 0.876 ; -; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.230 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; -; 6.257 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #762: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.221 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.304 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #763: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.647 ; 81 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.251 ; 3.259 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.223 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.251 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #764: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.882 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.277 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.304 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #765: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.046 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.263 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; -; 6.291 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; -; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #766: Setup slack is -0.704 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.160 ; -; Data Required Time ; 5.456 ; -; Slack ; -0.704 (VIOLATED) ; -+--------------------+--------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.162 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.160 ; 3.162 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|sload ; -; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.456 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y160_N8 ; ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #767: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.726 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.067 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; -; 6.097 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; -; 6.103 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; -; 6.233 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; -; 6.309 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #768: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.513 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.219 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.298 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #769: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.882 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.277 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.304 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #770: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.057 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.264 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; -; 6.290 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; -; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #771: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.160 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.162 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.160 ; 3.162 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|sload ; -; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y160_N58 ; ; vx_fetch|VX_Warp_zero|real_PC[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #772: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.778 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.210 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; -; 6.303 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #773: Setup slack is -0.703 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.703 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.546 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.572 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.578 ; 0.006 ; FF ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.280 ; 0.702 ; FF ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; -; 6.307 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #774: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.307 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.307 ; 3.309 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.280 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.307 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #775: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.775 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.397 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.477 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.255 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.283 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #776: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.840 ; 87 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.227 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.256 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #777: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.923 ; 89 ; 0.114 ; 1.372 ; -; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.268 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.298 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #778: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.317 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.319 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.346 ; 10 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.317 ; 3.319 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.317 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #779: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; -; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.301 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #780: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.317 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.319 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.346 ; 10 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.317 ; 3.319 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.317 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #781: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.871 ; 87 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.266 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.296 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #782: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.682 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.251 ; 3.259 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.223 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.251 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #783: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.681 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.250 ; 3.258 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.222 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.250 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #784: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.276 ; 0.878 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.306 ; 0.030 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #785: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.212 ; -; Data Required Time ; 5.510 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.116 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.767 ; 86 ; 0.573 ; 0.870 ; -; Cell ; ; 10 ; 0.328 ; 10 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.212 ; 3.220 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.873 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; -; 3.993 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.999 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.635 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.662 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.666 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.536 ; 0.870 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5|dataf ; -; 5.562 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5|combout ; -; 5.566 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5~la_lab/laboutb[6] ; -; 6.139 ; 0.573 ; FF ; IC ; 1 ; LABCELL_X51_Y153_N18 ; High Speed ; vx_d_e_reg|i498~5|datad ; -; 6.212 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X51_Y153_N18 ; High Speed ; vx_d_e_reg|i498~5|combout ; -; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5]|d ; -; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5] ; -; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.510 ; 0.164 ; ; uTsu ; 1 ; FF_X51_Y153_N19 ; ; vx_d_e_reg|csr_address[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #786: Setup slack is -0.702 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.337 ; -; Data Required Time ; 5.635 ; -; Slack ; -0.702 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.095 ; ; ; ; ; ; -; Data Delay ; 2.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.886 ; 83 ; 0.392 ; 0.786 ; -; Cell ; ; 8 ; 0.253 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; -; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; 6.337 ; 2.278 ; ; ; ; ; ; data path ; -; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; -; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; -; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; -; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.251 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; -; 6.337 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; -; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #787: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.304 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.850 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.302 ; 3.304 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.275 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.302 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #788: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.255 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.282 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #789: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[3] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.325 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.852 ; 86 ; 0.114 ; 0.795 ; -; Cell ; ; 16 ; 0.352 ; 11 ; 0.000 ; 0.063 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; -; 6.314 ; 3.325 ; ; ; ; ; ; data path ; -; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; -; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; -; 3.968 ; 0.795 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|dataf ; -; 3.997 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; -; 4.002 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; -; 4.429 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; -; 4.455 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.815 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.843 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.849 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.112 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.171 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.177 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.300 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.363 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.367 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.142 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.169 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.174 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.288 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.314 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #790: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.193 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.286 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #791: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.315 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.317 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.315 ; 3.317 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.289 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.315 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #792: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.302 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.304 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.302 ; 3.304 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.796 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.203 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.236 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.215 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; -; 6.302 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; -; 6.302 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; -; 6.302 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #793: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.679 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.248 ; 3.256 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.220 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #794: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.171 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.020 ; ; ; ; ; ; -; Data Delay ; 3.179 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.626 ; 83 ; 0.138 ; 1.398 ; -; Cell ; ; 10 ; 0.428 ; 13 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.171 ; 3.179 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 4.688 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; -; 4.768 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.773 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.171 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.171 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #795: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.823 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.275 ; 0.739 ; FF ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; -; 6.303 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #796: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.821 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.271 ; 0.917 ; FF ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; -; 6.298 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #797: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.261 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; -; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #798: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.294 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.835 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.294 ; 3.296 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; -; 6.266 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; -; 6.294 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #799: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.546 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.696 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.432 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.165 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; -; 6.247 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.546 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y151_N59 ; ; vx_d_e_reg|b_reg_data[26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #800: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[25] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.334 ; -; Data Required Time ; 5.633 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.883 ; 83 ; 0.308 ; 0.887 ; -; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; 6.334 ; 2.262 ; ; ; ; ; ; data path ; -; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; -; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; -; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.250 ; 0.308 ; FF ; IC ; 1 ; LABCELL_X73_Y157_N24 ; High Speed ; vx_fetch|VX_Warp_two|i199~22|datac ; -; 6.334 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X73_Y157_N24 ; High Speed ; vx_fetch|VX_Warp_two|i199~22|combout ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25]|d ; -; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25] ; -; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.633 ; 0.198 ; ; uTsu ; 1 ; FF_X73_Y157_N26 ; ; vx_fetch|VX_Warp_two|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #801: Setup slack is -0.701 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.701 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.385 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.269 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; -; 6.295 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #802: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[9] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.586 ; 79 ; 0.120 ; 0.774 ; -; Cell ; ; 16 ; 0.434 ; 13 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 6.201 ; 3.254 ; ; ; ; ; ; data path ; -; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; -; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; -; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; -; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; -; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; -; 4.236 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33|dataf ; -; 4.263 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33|combout ; -; 4.269 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33~la_mlab/laboutb[17] ; -; 4.389 ; 0.120 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datad ; -; 4.470 ; 0.081 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.474 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.691 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.766 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.770 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.203 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.230 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.393 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.421 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.426 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.173 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.201 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #803: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 84 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.026 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.053 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.059 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.230 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.306 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #804: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.873 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.531 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.255 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #805: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.887 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.264 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.291 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #806: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.838 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.218 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.305 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #807: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.512 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.269 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #808: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.818 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.256 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #809: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.472 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.499 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.504 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.255 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.283 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #810: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.773 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.451 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.171 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.301 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #811: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.757 ; 84 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.423 ; 13 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.165 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.299 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #812: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.385 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.412 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.416 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.191 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.284 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #813: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; -; Cell ; ; 12 ; 0.345 ; 10 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.304 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #814: Setup slack is -0.700 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.700 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.213 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.305 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; -; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #815: Setup slack is -0.699 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.699 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.346 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.426 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.430 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.244 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #816: Setup slack is -0.699 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.699 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.797 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.379 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.262 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.291 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.295 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.203 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.295 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #817: Setup slack is -0.699 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.699 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.343 ; 10 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.314 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #818: Setup slack is -0.699 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.699 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.871 ; 87 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.266 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.296 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #819: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 84 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.026 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.053 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.059 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.230 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.306 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #820: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.889 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.269 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #821: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.886 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.265 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.292 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #822: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.281 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.309 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #823: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.901 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.280 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.308 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #824: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.211 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.298 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #825: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.847 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.273 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.301 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #826: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.306 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.304 ; 3.306 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.277 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.304 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #827: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.254 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.281 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #828: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.269 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.297 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #829: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.462 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.466 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.264 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.291 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #830: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.873 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.254 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.282 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #831: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.271 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.298 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #832: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_f_d_reg|curr_PC[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.722 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.166 ; 3.168 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.166 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #833: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_f_d_reg|curr_PC[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.722 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.166 ; 3.168 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.166 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #834: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.296 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #835: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.824 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.258 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; -; 6.285 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; -; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; -; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #836: Setup slack is -0.698 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.698 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.418 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.212 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; -; 6.298 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #837: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.663 ; 82 ; 0.127 ; 0.734 ; -; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.246 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.218 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.246 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #838: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.662 ; 82 ; 0.127 ; 0.734 ; -; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.245 ; 3.253 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.217 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.245 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #839: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.087 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.572 ; 79 ; 0.120 ; 0.863 ; -; Cell ; ; 16 ; 0.492 ; 15 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 6.198 ; 3.246 ; ; ; ; ; ; data path ; -; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; -; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; -; 4.041 ; 0.863 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44|dataf ; -; 4.070 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44|combout ; -; 4.075 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44~la_mlab/laboutb[4] ; -; 4.195 ; 0.120 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|datac ; -; 4.281 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|combout ; -; 4.287 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45~la_mlab/laboutb[16] ; -; 4.419 ; 0.132 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datac ; -; 4.505 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; -; 4.511 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; -; 4.631 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; -; 4.763 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.767 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.200 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.227 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.233 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.390 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.418 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.423 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.170 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.198 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #840: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.089 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.118 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.124 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.247 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.306 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #841: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 85 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.218 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.245 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #842: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 83 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.437 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.913 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.939 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.945 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.223 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.296 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #843: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #844: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #845: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.890 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.268 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.296 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #846: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.663 ; 81 ; 0.136 ; 0.714 ; -; Cell ; ; 14 ; 0.518 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.299 ; 3.307 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.214 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.928 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.958 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.964 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.224 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.299 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #847: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.822 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.261 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #848: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.810 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.248 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #849: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.376 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.344 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.428 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.242 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #850: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.645 ; 80 ; 0.133 ; 0.712 ; -; Cell ; ; 14 ; 0.520 ; 16 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.283 ; 3.291 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.477 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.503 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.509 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.221 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.283 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #851: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.271 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.298 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #852: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; -; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.301 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #853: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.774 ; 84 ; 0.120 ; 1.302 ; -; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.179 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.296 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #854: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.421 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.211 ; 0.719 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; -; 6.301 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #855: Setup slack is -0.697 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[0] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.697 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.110 ; ; ; ; ; ; -; Data Delay ; 2.219 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 1.847 ; 83 ; 0.895 ; 0.952 ; -; Cell ; ; 6 ; 0.188 ; 8 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; 6.292 ; 2.219 ; ; ; ; ; ; data path ; -; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; -; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; -; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; -; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; -; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; -; 6.233 ; 0.895 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N36 ; High Speed ; vx_fetch|VX_Warp_two|i199~1|datae ; -; 6.292 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N36 ; High Speed ; vx_fetch|VX_Warp_two|i199~1|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0] ; -; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.162 ; ; uTsu ; 1 ; FF_X69_Y156_N38 ; ; vx_fetch|VX_Warp_two|real_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #856: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.660 ; 82 ; 0.127 ; 0.734 ; -; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.243 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.215 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.243 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #857: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #858: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #859: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.313 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.315 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.906 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.313 ; 3.315 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.285 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.313 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.313 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.313 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #860: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.314 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.316 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.314 ; 3.316 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.221 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.314 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #861: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.267 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.295 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #862: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.366 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.188 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.281 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #863: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.819 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.391 ; 0.474 ; RR ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.418 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.422 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.267 ; 0.845 ; FF ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.295 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #864: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.024 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.166 ; 3.168 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13]|sload ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13] ; -; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.026 ; ; uTsu ; 1 ; FF_X72_Y161_N35 ; ; vx_fetch|VX_Warp_zero|real_PC[13] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #865: Setup slack is -0.696 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.696 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.416 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.211 ; 0.686 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; -; 6.296 ; 0.085 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #866: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.294 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.302 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.681 ; 81 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.294 ; 3.302 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.141 ; 0.117 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.167 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.172 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.355 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.412 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.417 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.100 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.191 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.197 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.905 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.933 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.219 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.294 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #867: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.890 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.283 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.267 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.293 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #868: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.235 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.267 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.209 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.291 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #869: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.647 ; 81 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.479 ; 15 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.118 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; -; 6.246 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #870: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.221 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.308 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #871: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.289 ; 3.291 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.207 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.289 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #872: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.259 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.286 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #873: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.246 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #874: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.917 ; 89 ; 0.114 ; 1.366 ; -; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.262 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.290 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #875: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.294 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 85 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.294 ; 3.296 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.177 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.294 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #876: Setup slack is -0.695 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.471 ; -; Slack ; -0.695 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.024 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.166 ; 3.168 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19]|sload ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19] ; -; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.471 ; 0.027 ; ; uTsu ; 1 ; FF_X72_Y161_N53 ; ; vx_fetch|VX_Warp_zero|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #877: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #878: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #879: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.160 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.158 ; 3.160 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #880: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.300 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.302 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.828 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.300 ; 3.302 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.208 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.300 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.300 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.300 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #881: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.818 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.257 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.284 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #882: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.845 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.466 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.493 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.498 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.249 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #883: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.757 ; 84 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.419 ; 13 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.165 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.295 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #884: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.086 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.088 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.086 ; 3.088 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; -; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #885: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.086 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.088 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.086 ; 3.088 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; -; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #886: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.086 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.088 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.086 ; 3.088 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; -; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #887: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.309 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #888: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.293 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #889: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.309 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.311 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.309 ; 3.311 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.309 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #890: Setup slack is -0.694 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.694 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.865 ; 87 ; 0.104 ; 1.372 ; -; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.260 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.290 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #891: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.252 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.280 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #892: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.252 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.280 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #893: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.294 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.294 ; 3.296 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.267 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.294 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #894: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.819 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.247 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.274 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #895: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 82 ; 0.136 ; 0.708 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.292 ; 3.300 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.712 ; 0.549 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.740 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.744 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.880 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.959 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.964 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.320 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.410 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.098 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.189 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.195 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.903 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.931 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.937 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.217 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.292 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #896: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.219 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.306 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #897: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.205 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.287 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #898: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.854 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.249 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #899: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.903 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.266 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; -; 6.292 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #900: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.196 ; -; Data Required Time ; 5.503 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.463 ; 76 ; 0.121 ; 0.816 ; -; Cell ; ; 18 ; 0.662 ; 20 ; 0.000 ; 0.176 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; 6.196 ; 3.248 ; ; ; ; ; ; data path ; -; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; -; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; -; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; -; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; -; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; -; 4.247 ; 0.283 ; FF ; IC ; 5 ; LABCELL_X73_Y152_N0 ; High Speed ; vx_execute|[0].vx_alu|add_0~1|datac ; -; 4.423 ; 0.176 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N3 ; High Speed ; vx_execute|[0].vx_alu|add_0~5|cout ; -; 4.423 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|add_0~9|cin ; -; 4.440 ; 0.017 ; FR ; CELL ; 1 ; LABCELL_X73_Y152_N9 ; High Speed ; vx_execute|[0].vx_alu|add_0~13|cout ; -; 4.440 ; 0.000 ; RR ; CELL ; 3 ; LABCELL_X73_Y152_N12 ; High Speed ; vx_execute|[0].vx_alu|add_0~17|cin ; -; 4.451 ; 0.011 ; RF ; CELL ; 1 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|cout ; -; 4.451 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N18 ; High Speed ; vx_execute|[0].vx_alu|add_0~25|cin ; -; 4.565 ; 0.114 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29|sumout ; -; 4.570 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29~la_lab/laboutt[15] ; -; 4.997 ; 0.427 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|datac ; -; 5.084 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|combout ; -; 5.090 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51~la_mlab/laboutt[13] ; -; 5.211 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datac ; -; 5.301 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; -; 5.307 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; -; 6.123 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; -; 6.196 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #901: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.764 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.194 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; -; 6.276 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #902: Setup slack is -0.693 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[0] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.693 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.110 ; ; ; ; ; ; -; Data Delay ; 2.214 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 1.841 ; 83 ; 0.889 ; 0.952 ; -; Cell ; ; 6 ; 0.189 ; 9 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; -; 6.287 ; 2.214 ; ; ; ; ; ; data path ; -; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; -; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; -; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; -; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; -; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; -; 6.227 ; 0.889 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N54 ; High Speed ; vx_fetch|VX_Warp_three|i199~1|datae ; -; 6.287 ; 0.060 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N54 ; High Speed ; vx_fetch|VX_Warp_three|i199~1|combout ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0]|d ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0] ; -; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.161 ; ; uTsu ; 1 ; FF_X69_Y156_N56 ; ; vx_fetch|VX_Warp_three|real_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #903: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.149 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.151 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.149 ; 3.151 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #904: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.199 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.281 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #905: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.220 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.306 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #906: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.235 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.267 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.204 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.286 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #907: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.523 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.247 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.274 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #908: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.256 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #909: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.299 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.297 ; 3.299 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.210 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.297 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.297 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.297 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #910: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.552 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.647 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.118 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; -; 6.244 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #911: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.246 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #912: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.255 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #913: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.294 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.294 ; 3.296 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.268 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.294 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #914: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.246 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #915: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.682 ; 83 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.241 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.213 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.241 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #916: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.681 ; 83 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.240 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.212 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.240 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #917: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.296 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #918: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.774 ; 84 ; 0.120 ; 1.302 ; -; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.179 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.298 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #919: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.248 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; -; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #920: Setup slack is -0.692 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.692 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.254 ; 0.783 ; FF ; IC ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|dataf ; -; 6.282 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y161_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #921: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.251 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.279 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #922: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.251 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.279 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #923: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.734 ; 83 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.922 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.951 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.957 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.220 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.293 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #924: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.883 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.264 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.290 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #925: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.199 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.281 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #926: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.868 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.247 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.274 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #927: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.208 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.291 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #928: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.218 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.246 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #929: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.679 ; 83 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.238 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.210 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.238 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #930: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.435 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.461 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.198 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; -; 6.291 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; -; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #931: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.086 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.088 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.086 ; 3.088 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; -; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #932: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.086 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.088 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.086 ; 3.088 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; -; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #933: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_f_d_reg|curr_PC[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.161 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.751 ; 87 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.159 ; 3.161 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.159 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #934: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_f_d_reg|curr_PC[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.161 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.751 ; 87 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.159 ; 3.161 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.159 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #935: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.393 ; 12 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.306 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #936: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.459 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.152 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.150 ; 3.152 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21]|sload ; -; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.459 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y159_N25 ; ; vx_fetch|VX_Warp_zero|real_PC[21] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #937: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.459 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.152 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.150 ; 3.152 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3]|sload ; -; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.459 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y159_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #938: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.262 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.290 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #939: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; -; 6.277 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; -; 6.303 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; -; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #940: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.819 ; 86 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.391 ; 0.474 ; RR ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.418 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.422 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.267 ; 0.845 ; FF ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.295 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #941: Setup slack is -0.691 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[0] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.691 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.607 ; 80 ; 0.132 ; 0.955 ; -; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.124 ; -; uTco ; ; 1 ; 0.227 ; 7 ; 0.227 ; 0.227 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 6.192 ; 3.245 ; ; ; ; ; ; data path ; -; 3.174 ; 0.227 ; FF ; uTco ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0]|q ; -; 3.221 ; 0.047 ; FF ; CELL ; 12 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]~la_lab/laboutb[1] ; -; 4.176 ; 0.955 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|dataa ; -; 4.300 ; 0.124 ; FR ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; -; 4.305 ; 0.005 ; RR ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; -; 4.437 ; 0.132 ; RR ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; -; 4.510 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.514 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.729 ; 0.215 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.792 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.796 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.244 ; 0.448 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.272 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.278 ; 0.006 ; RR ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.424 ; 0.146 ; RR ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.450 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.455 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.166 ; 0.711 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.192 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #942: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.303 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.305 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.353 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.303 ; 3.305 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.211 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.303 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #943: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.300 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.302 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.300 ; 3.302 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.272 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.300 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #944: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.273 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.301 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #945: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.203 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.290 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #946: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.261 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #947: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.257 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.284 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #948: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.289 ; 3.291 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.197 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.289 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #949: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.244 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #950: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.819 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.479 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.258 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.286 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #951: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.850 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.266 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.292 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #952: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.520 ; 78 ; 0.118 ; 0.683 ; -; Cell ; ; 14 ; 0.600 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.238 ; 3.246 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.602 ; 0.362 ; FF ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.630 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.634 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.212 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.238 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #953: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.776 ; 86 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.216 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.244 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #954: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.779 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.385 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.412 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.416 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.182 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.275 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #955: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.893 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.256 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; -; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #956: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.808 ; 86 ; 0.108 ; 0.943 ; -; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.215 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.245 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #957: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.809 ; 87 ; 0.108 ; 0.944 ; -; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.216 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.245 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #958: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.296 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.298 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.793 ; 85 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.296 ; 3.298 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.177 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.296 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #959: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[1] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+-----------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; 0.005 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.666 ; 80 ; 0.113 ; 0.777 ; -; Cell ; ; 16 ; 0.534 ; 16 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.129 ; 4 ; 0.129 ; 0.129 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]|clk ; -; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1] ; -; 6.304 ; 3.329 ; ; ; ; ; ; data path ; -; 3.104 ; 0.129 ; RR ; uTco ; 1 ; FF_X40_Y149_N38 ; ; vx_csr_handler|decode_csr_address[1]|q ; -; 3.167 ; 0.063 ; RR ; CELL ; 548 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]~la_lab/laboutb[5] ; -; 3.808 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|datae ; -; 3.883 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; -; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; -; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; -; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; -; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; -; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; -; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; -; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; -; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; -; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.278 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.304 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #960: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.304 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+-----------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; 0.005 ; ; ; ; ; ; -; Data Delay ; 3.329 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.734 ; 82 ; 0.113 ; 0.777 ; -; Cell ; ; 16 ; 0.469 ; 14 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+-------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|clk ; -; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; -; 6.304 ; 3.329 ; ; ; ; ; ; data path ; -; 3.101 ; 0.126 ; FF ; uTco ; 1 ; FF_X40_Y149_N28 ; ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|q ; -; 3.145 ; 0.044 ; FF ; CELL ; 363 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE~la_lab/laboutt[18] ; -; 3.854 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|dataf ; -; 3.883 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; -; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; -; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; -; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; -; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; -; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; -; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; -; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; -; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; -; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.278 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.304 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #961: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.822 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.256 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; -; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #962: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.245 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; -; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #963: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.292 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #964: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.628 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 2.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.985 ; 88 ; 0.421 ; 0.887 ; -; Cell ; ; 8 ; 0.130 ; 6 ; 0.000 ; 0.044 ; -; uTco ; ; 1 ; 0.131 ; 6 ; 0.131 ; 0.131 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; -; 6.318 ; 2.246 ; ; ; ; ; ; data path ; -; 4.203 ; 0.131 ; FF ; uTco ; 1 ; FF_X108_Y149_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|q ; -; 4.247 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]~la_lab/laboutt[17] ; -; 4.924 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataf ; -; 4.950 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 4.954 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.841 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.866 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.871 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.292 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.318 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.628 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #965: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.163 ; -; Data Required Time ; 5.473 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.165 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.705 ; 85 ; 0.119 ; 1.196 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.163 ; 3.165 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.163 ; 1.196 ; FF ; IC ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31]|ena ; -; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.473 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y157_N8 ; ; vx_f_d_reg|curr_PC[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #966: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.163 ; -; Data Required Time ; 5.473 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.165 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.705 ; 85 ; 0.119 ; 1.196 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.163 ; 3.165 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.163 ; 1.196 ; FF ; IC ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28]|ena ; -; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.473 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y157_N49 ; ; vx_f_d_reg|curr_PC[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #967: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[1] ; -; To Node ; vx_e_m_reg|alu_result[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.191 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.079 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.563 ; 79 ; 0.127 ; 0.659 ; -; Cell ; ; 16 ; 0.501 ; 15 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 6.191 ; 3.247 ; ; ; ; ; ; data path ; -; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; -; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; -; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; -; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; -; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; -; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; -; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; -; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; -; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.417 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; -; 5.444 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; -; 5.449 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; -; 6.108 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; -; 6.191 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #968: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.244 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; -; 6.272 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #969: Setup slack is -0.690 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.308 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.690 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.310 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.308 ; 3.310 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.281 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; -; 6.308 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; -; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #970: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.658 ; 81 ; 0.127 ; 0.734 ; -; Cell ; ; 14 ; 0.498 ; 15 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.275 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.469 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.495 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.501 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.213 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.275 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #971: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.149 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.151 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.149 ; 3.151 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #972: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.862 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.363 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.396 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.240 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.266 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #973: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.260 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.288 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #974: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.289 ; 3.291 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.200 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.229 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.233 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.198 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.289 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #975: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.860 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.487 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.516 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.522 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.241 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #976: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.301 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.303 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.836 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.301 ; 3.303 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.275 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.301 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #977: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.773 ; 85 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.213 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.242 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #978: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.293 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #979: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.152 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.150 ; 3.152 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15]|sload ; -; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y159_N17 ; ; vx_fetch|VX_Warp_zero|real_PC[15] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #980: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.292 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; -; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #981: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.318 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 2.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.985 ; 88 ; 0.421 ; 0.887 ; -; Cell ; ; 8 ; 0.130 ; 6 ; 0.000 ; 0.044 ; -; uTco ; ; 1 ; 0.131 ; 6 ; 0.131 ; 0.131 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; -; 6.318 ; 2.246 ; ; ; ; ; ; data path ; -; 4.203 ; 0.131 ; FF ; uTco ; 1 ; FF_X108_Y149_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|q ; -; 4.247 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]~la_lab/laboutt[17] ; -; 4.924 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataf ; -; 4.950 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 4.954 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.841 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.866 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.871 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.292 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.318 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; -; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #982: Setup slack is -0.689 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.689 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.202 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; -; 6.281 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #983: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.209 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.237 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #984: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.208 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.236 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #985: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.149 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.151 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.149 ; 3.151 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #986: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.838 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.256 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #987: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.306 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.308 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.306 ; 3.308 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.213 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.306 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #988: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.307 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.305 ; 3.307 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.277 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.305 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #989: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.289 ; 3.291 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.197 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.289 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #990: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.778 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.195 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.287 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #991: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.771 ; 85 ; 0.119 ; 0.877 ; -; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.214 ; 0.877 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; -; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #992: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.805 ; 86 ; 0.108 ; 0.940 ; -; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.212 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.242 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #993: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.129 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.131 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.129 ; 3.131 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; -; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #994: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.129 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.131 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.129 ; 3.131 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; -; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #995: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.129 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.131 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.129 ; 3.131 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; -; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #996: Setup slack is -0.688 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.310 ; -; Data Required Time ; 5.622 ; -; Slack ; -0.688 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.312 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.850 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.310 ; 3.312 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.283 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; -; 6.310 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; -; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #997: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.796 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.206 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.234 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #998: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.882 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.259 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.286 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #999: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.259 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.285 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1000: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.227 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.254 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.259 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.201 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.283 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1001: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.299 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.855 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.299 ; 3.301 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.273 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.299 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1002: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.243 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1003: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.838 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.243 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1004: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|a_reg_data[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.129 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.131 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.129 ; 3.131 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; -; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1005: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.152 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.154 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.730 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.152 ; 3.154 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.152 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.152 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1006: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.152 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.154 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.730 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.152 ; 3.154 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.152 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.152 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1007: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.859 ; 87 ; 0.104 ; 1.366 ; -; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.254 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.282 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1008: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.463 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.152 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.150 ; 3.152 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18]|sload ; -; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.463 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y159_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[18] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1009: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.768 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; -; 6.249 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; -; 6.276 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1010: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.758 ; 84 ; 0.106 ; 1.228 ; -; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.156 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; -; 6.276 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1011: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.463 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.152 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.150 ; 3.152 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2]|sload ; -; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.463 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y159_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1012: Setup slack is -0.687 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.687 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.643 ; 82 ; 0.192 ; 0.922 ; -; Cell ; ; 12 ; 0.475 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.210 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1013: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.292 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.294 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.292 ; 3.294 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.493 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.524 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.528 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.200 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.292 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1014: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.255 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1015: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.778 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.195 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.287 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1016: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.745 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.333 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.413 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.417 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.231 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.258 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1017: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.203 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1018: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.884 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.378 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.405 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.411 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.246 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; -; 6.272 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1019: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.076 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.377 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.407 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.411 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.213 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; -; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; -; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1020: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.246 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; -; 6.274 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1021: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.190 ; 0.264 ; RR ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; -; 5.218 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; -; 5.224 ; 0.006 ; FF ; CELL ; 29 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[1] ; -; 6.201 ; 0.977 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|datac ; -; 6.279 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.162 ; ; uTsu ; 1 ; FF_X102_Y162_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1022: Setup slack is -0.686 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.686 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.658 ; 82 ; 0.192 ; 0.922 ; -; Cell ; ; 12 ; 0.459 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.236 ; 3.244 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.209 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1023: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.244 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.272 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1024: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.244 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.272 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1025: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.466 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.256 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1026: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.868 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.418 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.449 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.453 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.251 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1027: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.291 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.293 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.900 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.291 ; 3.293 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.263 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; -; 6.291 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; -; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1028: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.100 ; -; Data Required Time ; 5.415 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.102 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.694 ; 87 ; 0.108 ; 0.829 ; -; Cell ; ; 10 ; 0.286 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.100 ; 3.102 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.100 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.100 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1029: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.810 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.239 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; -; 6.267 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1030: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|warp_num[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.240 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.648 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.471 ; 15 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.238 ; 3.240 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.117 ; 0.702 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N6 ; High Speed ; vx_d_e_reg|i602~4|datab ; -; 6.238 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N6 ; High Speed ; vx_d_e_reg|i602~4|combout ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4]|d ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N8 ; ; vx_d_e_reg|warp_num[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1031: Setup slack is -0.685 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.685 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.262 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.290 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; -; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1032: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.854 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; -; 6.261 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1033: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.191 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.273 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1034: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.298 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.300 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.298 ; 3.300 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.212 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.298 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1035: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.227 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.254 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.259 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.196 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.278 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1036: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.634 ; 81 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.478 ; 15 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.105 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; -; 6.232 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1037: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.373 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.253 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1038: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.248 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1039: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.235 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1040: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.677 ; 82 ; 0.133 ; 0.712 ; -; Cell ; ; 14 ; 0.474 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.270 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.464 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.490 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.496 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.208 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.270 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1041: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.100 ; -; Data Required Time ; 5.416 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.102 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.694 ; 87 ; 0.108 ; 0.829 ; -; Cell ; ; 10 ; 0.286 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.100 ; 3.102 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.100 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.100 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1042: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.764 ; 84 ; 0.110 ; 1.302 ; -; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.166 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.283 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1043: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.097 ; -; Data Required Time ; 5.413 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.126 ; ; ; ; ; ; -; Data Delay ; 3.120 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.747 ; 88 ; 0.541 ; 0.817 ; -; Cell ; ; 8 ; 0.250 ; 8 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.097 ; 3.120 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.730 ; 0.541 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datac ; -; 3.821 ; 0.091 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.827 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.504 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.531 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.535 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.247 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; -; 5.275 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; -; 5.280 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; -; 6.097 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; -; 6.097 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; -; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1044: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.758 ; 84 ; 0.106 ; 1.228 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.156 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; -; 6.273 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1045: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.860 ; 87 ; 0.106 ; 1.317 ; -; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.258 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; -; 6.284 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1046: Setup slack is -0.684 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.684 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.708 ; 82 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.456 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.190 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; -; 6.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1047: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.597 ; 80 ; 0.127 ; 0.668 ; -; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.204 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.232 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1048: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.231 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.233 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.596 ; 80 ; 0.127 ; 0.668 ; -; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.231 ; 3.233 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.203 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.231 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1049: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.881 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.334 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; -; 5.363 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; -; 5.367 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; -; 6.260 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; -; 6.287 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1050: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.229 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1051: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.825 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.256 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.282 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1052: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.191 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.273 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1053: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.810 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.239 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.266 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1054: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.800 ; 87 ; 0.108 ; 0.935 ; -; Cell ; ; 12 ; 0.314 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.206 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.234 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1055: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.153 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.155 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.731 ; 87 ; 0.116 ; 1.398 ; -; Cell ; ; 10 ; 0.303 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.153 ; 3.155 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.388 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.722 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.750 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.755 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.153 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1056: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.905 ; 89 ; 0.114 ; 1.354 ; -; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.250 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.278 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1057: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.859 ; 87 ; 0.106 ; 1.316 ; -; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.257 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; -; 6.283 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1058: Setup slack is -0.683 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.683 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.259 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; -; 6.287 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; -; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1059: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.594 ; 80 ; 0.127 ; 0.668 ; -; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.201 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.229 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1060: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.477 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.161 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.159 ; 3.161 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.477 ; 0.034 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1061: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.203 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.295 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1062: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 87 ; 0.119 ; 1.046 ; -; Cell ; ; 14 ; 0.299 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.271 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.297 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.303 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.243 ; 0.940 ; FF ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; -; 6.272 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1063: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.187 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.125 ; ; ; ; ; ; -; Data Delay ; 3.189 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.661 ; 83 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.406 ; 13 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.187 ; 3.189 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.114 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; -; 6.187 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.187 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.187 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1064: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.760 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.286 ; 3.288 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.313 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.343 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.347 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.200 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.286 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1065: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.295 ; 3.297 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.468 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.208 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.295 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1066: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.760 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.194 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.276 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1067: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.627 ; 81 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.230 ; 3.238 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.203 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.230 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1068: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.821 ; 87 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.208 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.236 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1069: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.644 ; 80 ; 0.142 ; 0.755 ; -; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.288 ; 3.296 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.008 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.035 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.041 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.212 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.288 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1070: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.243 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; -; 6.271 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1071: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.231 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.233 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.637 ; 82 ; 0.192 ; 0.916 ; -; Cell ; ; 12 ; 0.475 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.231 ; 3.233 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.204 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.231 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1072: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.607 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.291 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.711 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.289 ; 3.291 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.057 ; 0.642 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35|dataf ; -; 6.083 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35|combout ; -; 6.089 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35~la_mlab/laboutb[7] ; -; 6.212 ; 0.123 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|datae ; -; 6.289 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; -; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; -; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.607 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1073: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.764 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.196 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; -; 6.282 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1074: Setup slack is -0.682 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.682 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.257 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; -; 6.283 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1075: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.583 ; 79 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.565 ; 17 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.161 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.268 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1076: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.662 ; 81 ; 0.118 ; 0.734 ; -; Cell ; ; 14 ; 0.499 ; 15 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.280 ; 3.288 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.085 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.164 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.169 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.287 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.398 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.403 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.177 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.183 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.891 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.919 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.925 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.205 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.280 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1077: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.478 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.161 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.159 ; 3.161 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.478 ; 0.035 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1078: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.355 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.384 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.388 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.232 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.258 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1079: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.192 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.221 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.225 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.190 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.281 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1080: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.802 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.514 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.233 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1081: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.244 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1082: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.800 ; 87 ; 0.119 ; 0.877 ; -; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.207 ; 0.877 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; -; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1083: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.821 ; 87 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.208 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.236 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1084: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.905 ; 89 ; 0.114 ; 1.354 ; -; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.250 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.278 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1085: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.652 ; 82 ; 0.192 ; 0.916 ; -; Cell ; ; 12 ; 0.459 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.230 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.203 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1086: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.243 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; -; 6.271 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1087: Setup slack is -0.681 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.681 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.232 ; 0.739 ; FF ; IC ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|dataf ; -; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1088: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.583 ; 79 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.564 ; 17 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.161 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.267 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1089: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.667 ; 81 ; 0.117 ; 0.714 ; -; Cell ; ; 14 ; 0.498 ; 15 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.282 ; 3.290 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.141 ; 0.117 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.167 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.172 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.355 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.412 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.417 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.100 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.191 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.197 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.911 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.941 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.947 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.207 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.282 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1090: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.674 ; 82 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.473 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.160 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.267 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1091: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 85 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.460 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.486 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.492 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.204 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.266 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1092: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.479 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.161 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.159 ; 3.161 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.479 ; 0.036 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1093: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.515 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.234 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; -; 6.261 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1094: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.198 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; -; 6.284 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1095: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.284 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.286 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.779 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.284 ; 3.286 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.311 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.341 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.345 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.198 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.284 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1096: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_address[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.121 ; ; ; ; ; ; -; Data Delay ; 3.194 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.677 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.192 ; 3.194 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.336 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.119 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; -; 6.192 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1097: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.413 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.444 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.448 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.246 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1098: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.370 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.197 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.280 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1099: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.819 ; 87 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.206 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.234 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1100: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.902 ; 89 ; 0.114 ; 1.351 ; -; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.247 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; -; 6.275 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1101: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.296 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.644 ; 80 ; 0.142 ; 0.755 ; -; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.288 ; 3.296 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.008 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.035 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.041 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.212 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.288 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1102: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|b_reg_data[15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.558 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.240 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.740 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.238 ; 3.240 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.208 ; 0.794 ; FF ; IC ; 1 ; MLABCELL_X80_Y152_N57 ; High Speed ; vx_d_e_reg|i385~48|dataf ; -; 6.238 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X80_Y152_N57 ; High Speed ; vx_d_e_reg|i385~48|combout ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15]|d ; -; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.558 ; 0.170 ; ; uTsu ; 1 ; FF_X80_Y152_N59 ; ; vx_d_e_reg|b_reg_data[15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1103: Setup slack is -0.680 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.082 ; -; Data Required Time ; 5.402 ; -; Slack ; -0.680 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.090 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.547 ; 82 ; 0.142 ; 0.829 ; -; Cell ; ; 10 ; 0.418 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.082 ; 3.090 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.082 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.082 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1104: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.674 ; 82 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.160 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.266 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1105: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.874 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.253 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1106: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.872 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.252 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; -; 6.279 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1107: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.824 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.251 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1108: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.825 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.251 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; -; 6.277 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1109: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.455 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.484 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.489 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.195 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.274 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1110: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.745 ; 85 ; 0.108 ; 0.862 ; -; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.215 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; -; 6.243 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1111: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.744 ; 85 ; 0.108 ; 0.861 ; -; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.214 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; -; 6.243 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1112: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.233 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1113: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.821 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.255 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.281 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1114: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.816 ; 87 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.203 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.232 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1115: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.764 ; 84 ; 0.110 ; 1.302 ; -; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.166 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.285 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1116: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.659 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.227 ; 3.235 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.200 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.227 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1117: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.253 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1118: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.644 ; 82 ; 0.138 ; 0.922 ; -; Cell ; ; 12 ; 0.468 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.229 ; 3.237 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.202 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.229 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1119: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.082 ; -; Data Required Time ; 5.403 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.090 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.547 ; 82 ; 0.142 ; 0.829 ; -; Cell ; ; 10 ; 0.418 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.082 ; 3.090 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.082 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.082 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1120: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.205 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|datad ; -; 6.285 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|combout ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|d ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1121: Setup slack is -0.679 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.679 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.817 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.249 ; 0.735 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|dataf ; -; 6.275 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1122: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.818 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.256 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.283 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1123: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.741 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.373 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.453 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.458 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.231 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.259 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1124: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.288 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 82 ; 0.136 ; 0.714 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.280 ; 3.288 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.712 ; 0.549 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.740 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.744 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.880 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.959 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.964 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.320 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.410 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.098 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.189 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.195 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.909 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.939 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.945 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.205 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.280 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1125: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.228 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.230 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.795 ; 87 ; 0.108 ; 0.930 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.228 ; 3.230 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.201 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.228 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.228 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.228 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1126: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.837 ; 87 ; 0.114 ; 1.378 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.242 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.272 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1127: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.253 ; 0.685 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1128: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|rs1[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.546 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.084 ; ; ; ; ; ; -; Data Delay ; 3.226 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.678 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.427 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.139 ; 79 ; 0.000 ; 2.139 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.224 ; 3.226 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.147 ; 0.732 ; FF ; IC ; 1 ; LABCELL_X81_Y156_N33 ; High Speed ; vx_d_e_reg|i316~2|datac ; -; 6.224 ; 0.077 ; FR ; CELL ; 1 ; LABCELL_X81_Y156_N33 ; High Speed ; vx_d_e_reg|i316~2|combout ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2]|d ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.414 ; 2.914 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.204 ; 2.139 ; RR ; IC ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2]|clk ; -; 5.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2] ; -; 5.414 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.384 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.546 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y156_N35 ; ; vx_d_e_reg|rs1[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1129: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.708 ; 82 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.456 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.190 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; -; 6.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X103_Y161_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1130: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.253 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X99_Y145_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1131: Setup slack is -0.678 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[7] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.678 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 83 ; 0.122 ; 1.025 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; -; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; -; 6.277 ; 3.284 ; ; ; ; ; ; data path ; -; 3.116 ; 0.123 ; RR ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; -; 3.212 ; 0.096 ; RR ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; -; 4.237 ; 1.025 ; RR ; IC ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|datac ; -; 4.330 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|combout ; -; 4.336 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174~la_mlab/laboutt[3] ; -; 4.481 ; 0.145 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datae ; -; 4.556 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; -; 4.561 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; -; 5.077 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; -; 5.103 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.107 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.234 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.321 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.098 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.124 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.251 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.277 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1132: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.697 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.276 ; 3.284 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.887 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.915 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.921 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.201 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.276 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1133: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.466 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.245 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.273 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1134: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.864 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.241 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1135: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.240 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; -; 6.268 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1136: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.859 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.237 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; -; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1137: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.184 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.276 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1138: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.079 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.453 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.482 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.487 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.193 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.272 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1139: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.871 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.378 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.405 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.411 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.233 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1140: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.094 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.188 ; 0.635 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|datac ; -; 6.282 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1141: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.053 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.744 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.227 ; 0.705 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|clk ; -; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y162_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1142: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.033 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.446 ; 0.529 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.518 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.522 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.248 ; 0.726 ; FF ; IC ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|dataf ; -; 6.276 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|combout ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|d ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.164 ; ; uTsu ; 1 ; FF_X105_Y157_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1143: Setup slack is -0.677 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.677 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.201 ; 0.604 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|datad ; -; 6.281 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|combout ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|d ; -; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y147_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1144: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.857 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.237 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; -; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1145: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.287 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.287 ; 3.289 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.207 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; -; 6.287 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; -; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1146: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.870 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.248 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; -; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1147: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.796 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; -; 6.253 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1148: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.758 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.488 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.245 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1149: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.254 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1150: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.760 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.451 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.229 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.257 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1151: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.262 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.288 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1152: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.743 ; 85 ; 0.108 ; 0.876 ; -; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.202 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; -; 6.229 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; -; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; -; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1153: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.794 ; 86 ; 0.108 ; 0.929 ; -; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.230 ; 3.232 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.201 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.230 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1154: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.070 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.068 ; 3.070 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1155: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.070 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.068 ; 3.070 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1156: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.070 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.068 ; 3.070 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1157: Setup slack is -0.676 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.676 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.856 ; 87 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.240 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.270 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1158: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.592 ; 79 ; 0.127 ; 0.712 ; -; Cell ; ; 14 ; 0.550 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.455 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.481 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.487 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.199 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.261 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1159: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.702 ; 82 ; 0.107 ; 0.854 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.066 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; -; 6.094 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; -; 6.100 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; -; 6.207 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; -; 6.283 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1160: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.710 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.039 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; -; 6.069 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; -; 6.075 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; -; 6.205 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; -; 6.281 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1161: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.823 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.326 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; -; 5.355 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; -; 5.359 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; -; 6.252 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; -; 6.279 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1162: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.746 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.221 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1163: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[28] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.176 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.087 ; ; ; ; ; ; -; Data Delay ; 3.224 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.551 ; 79 ; 0.120 ; 0.813 ; -; Cell ; ; 16 ; 0.492 ; 15 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.181 ; 6 ; 0.181 ; 0.181 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 6.176 ; 3.224 ; ; ; ; ; ; data path ; -; 3.133 ; 0.181 ; FF ; uTco ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28]|q ; -; 3.177 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]~la_lab/laboutb[14] ; -; 3.990 ; 0.813 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|dataf ; -; 4.017 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|combout ; -; 4.022 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41~la_lab/laboutb[11] ; -; 4.179 ; 0.157 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datac ; -; 4.263 ; 0.084 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; -; 4.269 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; -; 4.393 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; -; 4.483 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; -; 4.489 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; -; 4.609 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; -; 4.741 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.745 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.178 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.205 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.211 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.368 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.396 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.401 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.148 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.176 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.176 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.176 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1164: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.184 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.276 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1165: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.847 ; 87 ; 0.104 ; 1.354 ; -; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.242 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.270 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1166: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.837 ; 87 ; 0.114 ; 1.378 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.242 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.272 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1167: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.724 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.276 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; -; 5.355 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; -; 5.359 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; -; 6.206 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; -; 6.293 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1168: Setup slack is -0.675 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.675 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.724 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.276 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; -; 5.355 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; -; 5.359 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; -; 6.206 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; -; 6.293 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|d ; -; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1169: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.222 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.230 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.640 ; 82 ; 0.127 ; 0.734 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.222 ; 3.230 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.195 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.222 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1170: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.723 ; 83 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.273 ; 3.281 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.884 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.912 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.198 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.273 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1171: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.596 ; 79 ; 0.118 ; 0.708 ; -; Cell ; ; 14 ; 0.558 ; 17 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.078 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.280 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.391 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.396 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.079 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.170 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.884 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.912 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.198 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.273 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1172: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.865 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.366 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.399 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.243 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.272 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1173: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.249 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.277 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1174: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.374 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.486 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.243 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1175: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.253 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.280 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1176: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.230 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1177: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.407 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.438 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.442 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.240 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.267 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1178: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.001 ; ; ; ; ; ; -; Data Delay ; 3.309 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.725 ; 82 ; 0.122 ; 0.789 ; -; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|clk ; -; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; -; 6.272 ; 3.309 ; ; ; ; ; ; data path ; -; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N43 ; ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|q ; -; 3.175 ; 0.085 ; RR ; CELL ; 230 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE~la_lab/laboutb[8] ; -; 3.964 ; 0.789 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|dataa ; -; 4.082 ; 0.118 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; -; 4.086 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; -; 4.347 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; -; 4.375 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; -; 4.380 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; -; 5.035 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; -; 5.121 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.127 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.250 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.313 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.317 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.092 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.119 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.124 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.246 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.272 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1179: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.177 ; -; Data Required Time ; 5.503 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.659 ; 82 ; 0.124 ; 0.816 ; -; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; 6.177 ; 3.229 ; ; ; ; ; ; data path ; -; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; -; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; -; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; -; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; -; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; -; 4.423 ; 0.459 ; FF ; IC ; 1 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28|datac ; -; 4.509 ; 0.086 ; FF ; CELL ; 1 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28|combout ; -; 4.513 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28~la_lab/laboutb[12] ; -; 4.741 ; 0.228 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49|datac ; -; 4.828 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49~la_mlab/laboutt[0] ; -; 4.958 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|dataf ; -; 4.983 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; -; 4.989 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; -; 5.205 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; -; 5.282 ; 0.077 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; -; 5.288 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; -; 6.104 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; -; 6.177 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; -; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; -; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1180: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; -; Cell ; ; 12 ; 0.405 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.272 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1181: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.699 ; 83 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.444 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.552 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.179 ; 0.627 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|datac ; -; 6.262 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|combout ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|d ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y165_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1182: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.223 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.638 ; 82 ; 0.138 ; 0.916 ; -; Cell ; ; 12 ; 0.468 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.223 ; 3.231 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.196 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.223 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1183: Setup slack is -0.674 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.674 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.235 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|dataf ; -; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X97_Y165_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1184: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.746 ; 84 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.889 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.915 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.921 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.199 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.272 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1185: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.752 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.181 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1186: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.366 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.444 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.448 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; -; 6.234 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; -; 6.261 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1187: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.393 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.470 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.474 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.242 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1188: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_address[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.185 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.121 ; ; ; ; ; ; -; Data Delay ; 3.187 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.706 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.185 ; 3.187 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.112 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; -; 6.185 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; -; 6.185 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; -; 6.185 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1189: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.786 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.320 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.400 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.404 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.218 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1190: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.070 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.068 ; 3.070 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1191: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.070 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.068 ; 3.070 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1192: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.847 ; 87 ; 0.104 ; 1.354 ; -; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.242 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.270 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1193: Setup slack is -0.673 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.673 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.856 ; 87 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.240 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.270 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1194: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.046 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.231 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; -; 6.259 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; -; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1195: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.507 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.226 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; -; 6.253 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1196: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.190 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; -; 6.276 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; -; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1197: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.234 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; -; 6.262 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1198: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.247 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.275 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1199: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.251 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.278 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1200: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.420 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.447 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.453 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.243 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1201: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.844 ; 87 ; 0.104 ; 1.351 ; -; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.239 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; -; 6.267 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1202: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.385 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.270 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1203: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.177 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.104 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.767 ; 86 ; 0.555 ; 0.986 ; -; Cell ; ; 10 ; 0.310 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.177 ; 3.200 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; FF ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.169 ; 0.069 ; FF ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.724 ; 0.555 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datac ; -; 3.817 ; 0.093 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.823 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.459 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.486 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.490 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.476 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; -; 5.503 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; -; 5.508 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; -; 6.098 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; -; 6.177 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1204: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.509 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.232 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1205: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 81 ; 0.192 ; 0.667 ; -; Cell ; ; 14 ; 0.509 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.232 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1206: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.662 ; 82 ; 0.142 ; 0.944 ; -; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.227 ; 3.235 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.198 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.227 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1207: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.621 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.265 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|dataf ; -; 6.293 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.621 ; 0.182 ; ; uTsu ; 1 ; FF_X107_Y153_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1208: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.661 ; 82 ; 0.142 ; 0.943 ; -; Cell ; ; 12 ; 0.449 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.227 ; 3.235 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.197 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.227 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1209: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[25] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.305 ; -; Data Required Time ; 5.633 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.108 ; ; ; ; ; ; -; Data Delay ; 2.233 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.911 ; 86 ; 0.336 ; 0.887 ; -; Cell ; ; 8 ; 0.189 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; -; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; -; 6.305 ; 2.233 ; ; ; ; ; ; data path ; -; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; -; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; -; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.278 ; 0.336 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~20|dataf ; -; 6.305 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~20|combout ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25]|d ; -; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N17 ; ; vx_fetch|VX_Warp_one|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1210: Setup slack is -0.672 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.293 ; -; Data Required Time ; 5.621 ; -; Slack ; -0.672 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.295 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.293 ; 3.295 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.265 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|dataf ; -; 6.293 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|combout ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]|d ; -; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.621 ; 0.182 ; ; uTsu ; 1 ; FF_X107_Y153_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1211: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.178 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; -; 6.271 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1212: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.244 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; -; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1213: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.245 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; -; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1214: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.767 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.243 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; -; 6.269 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1215: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.235 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1216: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.222 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.249 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1217: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.805 ; 86 ; 0.106 ; 1.302 ; -; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.153 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.270 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1218: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.647 ; 81 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.259 ; 3.267 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.231 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.259 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1219: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.647 ; 81 ; 0.192 ; 0.682 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.259 ; 3.267 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.231 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.259 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1220: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.746 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.480 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; -; 6.226 ; 0.746 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~617|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~617|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1221: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.184 ; 0.616 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|datac ; -; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1222: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.094 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.178 ; 0.579 ; RR ; IC ; 1 ; MLABCELL_X94_Y145_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~536|datac ; -; 6.272 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X94_Y145_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~536|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X94_Y145_N59 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1223: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[1] ; -; To Node ; vx_e_m_reg|alu_result[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.134 ; -; Data Required Time ; 5.463 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.190 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.540 ; 80 ; 0.187 ; 0.673 ; -; Cell ; ; 14 ; 0.467 ; 15 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 6.134 ; 3.190 ; ; ; ; ; ; data path ; -; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; -; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; -; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; -; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; -; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; -; 4.254 ; 0.402 ; FF ; IC ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25|datac ; -; 4.341 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25|combout ; -; 4.347 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25~la_mlab/laboutb[17] ; -; 4.794 ; 0.447 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26|datac ; -; 4.881 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26|combout ; -; 4.887 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26~la_mlab/laboutt[8] ; -; 5.074 ; 0.187 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27|dataf ; -; 5.100 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27|combout ; -; 5.105 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27~la_lab/laboutt[9] ; -; 5.311 ; 0.206 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28|datae ; -; 5.373 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28|combout ; -; 5.377 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28~la_lab/laboutt[8] ; -; 6.050 ; 0.673 ; FF ; IC ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|datae ; -; 6.134 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|combout ; -; 6.134 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|d ; -; 6.134 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.363 ; 2.863 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|clk ; -; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; -; 5.363 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.333 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.463 ; 0.130 ; ; uTsu ; 1 ; FF_X45_Y153_N22 ; ; vx_e_m_reg|alu_result[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1224: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.237 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~991|dataf ; -; 6.266 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~991|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1225: Setup slack is -0.671 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.671 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.729 ; 83 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.423 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.179 ; 0.654 ; FF ; IC ; 1 ; MLABCELL_X107_Y152_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~964|datac ; -; 6.271 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X107_Y152_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~964|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1226: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[3] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.286 ; -; Data Required Time ; 5.616 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.297 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.769 ; 84 ; 0.122 ; 0.775 ; -; Cell ; ; 16 ; 0.407 ; 12 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; -; 6.286 ; 3.297 ; ; ; ; ; ; data path ; -; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; -; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; -; 3.863 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|dataf ; -; 3.891 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; -; 3.897 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; -; 4.338 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; -; 4.419 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.424 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.779 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.807 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.813 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.076 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.135 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.141 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.264 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.327 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.331 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.106 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.133 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.138 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.260 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.286 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1227: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 84 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.040 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.069 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.075 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.203 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.279 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1228: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.111 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.113 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.111 ; 3.113 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; -; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1229: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.111 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.113 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.111 ; 3.113 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; -; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1230: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.111 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.113 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.111 ; 3.113 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; -; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1231: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.406 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.285 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1232: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; -; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.269 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1233: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.285 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.287 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.406 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.285 ; 3.287 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.285 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1234: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.831 ; 87 ; 0.114 ; 1.372 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.236 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.266 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1235: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.779 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.231 ; 0.696 ; FF ; IC ; 1 ; LABCELL_X93_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~664|dataf ; -; 6.260 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X93_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~664|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1236: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.658 ; 82 ; 0.142 ; 0.940 ; -; Cell ; ; 12 ; 0.449 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.224 ; 3.232 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.194 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.224 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1237: Setup slack is -0.670 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.670 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.290 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.288 ; 3.290 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.261 ; 0.767 ; FF ; IC ; 1 ; MLABCELL_X105_Y151_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~921|dataf ; -; 6.288 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y151_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~921|combout ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25]|d ; -; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X105_Y151_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1238: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 84 ; 0.108 ; 0.787 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.030 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.057 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.063 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.201 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.279 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1239: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1240: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1241: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.501 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.229 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1242: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.331 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.237 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; -; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1243: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.229 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1244: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; -; 6.234 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; -; 6.262 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1245: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.232 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; -; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1246: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.233 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1247: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.758 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.397 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.473 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.243 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1248: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.750 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.300 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.330 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.334 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.187 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.273 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1249: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.223 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.250 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1250: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.455 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.195 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.282 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1251: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.181 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.263 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1252: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.225 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.252 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1253: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.223 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.756 ; 85 ; 0.108 ; 0.888 ; -; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.223 ; 3.225 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.196 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; -; 6.223 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; -; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; -; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1254: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.001 ; ; ; ; ; ; -; Data Delay ; 3.301 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.717 ; 82 ; 0.114 ; 0.789 ; -; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|clk ; -; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; -; 6.264 ; 3.301 ; ; ; ; ; ; data path ; -; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N43 ; ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|q ; -; 3.175 ; 0.085 ; RR ; CELL ; 230 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE~la_lab/laboutb[8] ; -; 3.964 ; 0.789 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|dataa ; -; 4.082 ; 0.118 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; -; 4.086 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; -; 4.347 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; -; 4.375 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; -; 4.380 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; -; 5.035 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; -; 5.121 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.127 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.250 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.313 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.317 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.092 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.119 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.124 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.238 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.264 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1255: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.217 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.659 ; 82 ; 0.133 ; 0.657 ; -; Cell ; ; 14 ; 0.439 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.217 ; 3.225 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; -; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.190 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.217 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1256: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.894 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.257 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; -; 6.283 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; -; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1257: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|a_reg_data[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.111 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.113 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.111 ; 3.113 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; -; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1258: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_f_d_reg|curr_PC[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.137 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.139 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.715 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.137 ; 3.139 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.137 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; -; 6.137 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1259: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_f_d_reg|curr_PC[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.137 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.139 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.715 ; 86 ; 0.119 ; 1.282 ; -; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.137 ; 3.139 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.137 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; -; 6.137 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1260: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.687 ; 82 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.475 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.252 ; 0.326 ; RR ; IC ; 1 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|datac ; -; 5.331 ; 0.079 ; RF ; CELL ; 2 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|combout ; -; 5.336 ; 0.005 ; FF ; CELL ; 9 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19~la_lab/laboutb[17] ; -; 6.189 ; 0.853 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~610|datad ; -; 6.281 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X101_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~610|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.175 ; ; uTsu ; 1 ; FF_X101_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1261: Setup slack is -0.669 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.669 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.563 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.188 ; 0.625 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~590|datad ; -; 6.268 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X102_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~590|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1262: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[4] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.169 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.584 ; 80 ; 0.125 ; 0.747 ; -; Cell ; ; 16 ; 0.515 ; 16 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4] ; -; 6.169 ; 3.221 ; ; ; ; ; ; data path ; -; 3.070 ; 0.122 ; FF ; uTco ; 1 ; FF_X79_Y153_N43 ; ; vx_d_e_reg|b_reg_data[4]|q ; -; 3.138 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]~la_lab/laboutb[8] ; -; 3.884 ; 0.746 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|dataf ; -; 3.911 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|combout ; -; 3.915 ; 0.004 ; FF ; CELL ; 42 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18~la_lab/laboutb[2] ; -; 4.074 ; 0.159 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29|datab ; -; 4.183 ; 0.109 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29|combout ; -; 4.187 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29~la_lab/laboutt[16] ; -; 4.312 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datab ; -; 4.438 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.442 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.659 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.734 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.738 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.171 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.198 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.204 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.361 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.389 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.394 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.141 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.169 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.169 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.169 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1263: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1264: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1265: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.506 ; 76 ; 0.118 ; 0.755 ; -; Cell ; ; 14 ; 0.650 ; 20 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.274 ; 3.282 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.994 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.021 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.027 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.198 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.274 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1266: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.752 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.181 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1267: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.865 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.366 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.399 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.243 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.272 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1268: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 88 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.235 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; -; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1269: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.229 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1270: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.723 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.436 ; 13 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.199 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; -; 6.279 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; -; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; -; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1271: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.501 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.240 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; -; 6.267 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1272: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.462 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.494 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.499 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.223 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1273: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.232 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1274: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.746 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.456 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.485 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.490 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.186 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.273 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1275: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.231 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.258 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1276: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.767 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.353 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.315 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.395 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.399 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.213 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1277: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.768 ; 85 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.377 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.408 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.413 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.133 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; -; 6.267 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1278: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.353 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.380 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.384 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.159 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; -; 6.252 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1279: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; -; Cell ; ; 12 ; 0.405 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.272 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1280: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.386 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.283 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1281: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.267 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1282: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.386 ; 12 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.283 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1283: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.850 ; 87 ; 0.104 ; 1.372 ; -; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.234 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.264 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1284: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_csr_handler|decode_csr_address[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.166 ; -; Data Required Time ; 5.498 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.141 ; ; ; ; ; ; -; Data Delay ; 3.174 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.836 ; 89 ; 0.630 ; 0.817 ; -; Cell ; ; 8 ; 0.211 ; 7 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.166 ; 3.174 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.810 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; -; 3.890 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; -; 3.896 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; -; 4.573 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; -; 4.600 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; -; 4.604 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; -; 5.316 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; -; 5.344 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; -; 5.349 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; -; 6.166 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|d ; -; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|clk ; -; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; -; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.498 ; 0.177 ; ; uTsu ; 1 ; FF_X38_Y157_N17 ; ; vx_csr_handler|decode_csr_address[4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1285: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.046 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.179 ; 0.579 ; RR ; IC ; 1 ; MLABCELL_X94_Y160_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~877|datad ; -; 6.266 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X94_Y160_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~877|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13]|clk ; -; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; -; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.176 ; ; uTsu ; 1 ; FF_X94_Y160_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1286: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.290 ; -; Data Required Time ; 5.622 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.292 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.290 ; 3.292 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.261 ; 0.738 ; FF ; IC ; 1 ; MLABCELL_X107_Y149_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~761|dataf ; -; 6.290 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X107_Y149_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~761|combout ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25]|d ; -; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1287: Setup slack is -0.668 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.297 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.668 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.101 ; ; ; ; ; ; -; Data Delay ; 2.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 76 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.849 ; 83 ; 0.403 ; 0.782 ; -; Cell ; ; 8 ; 0.226 ; 10 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.162 ; 7 ; 0.162 ; 0.162 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.060 ; 3.060 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.060 ; 2.317 ; FF ; IC ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]|clk ; -; 4.060 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; -; 6.297 ; 2.237 ; ; ; ; ; ; data path ; -; 4.222 ; 0.162 ; FF ; uTco ; 1 ; FF_X92_Y142_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]|q ; -; 4.265 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[5] ; -; 5.047 ; 0.782 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datac ; -; 5.132 ; 0.085 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; -; 5.138 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; -; 5.802 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; -; 5.830 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; -; 5.835 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; -; 6.238 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; -; 6.297 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; -; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1288: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.654 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.905 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.911 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.191 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.266 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1289: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 82 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.471 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.147 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.254 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1290: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.898 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.927 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.933 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.196 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.269 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1291: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.866 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.243 ; 0.675 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; -; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1292: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.372 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.395 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.471 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.475 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.241 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1293: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.221 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1294: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.631 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.468 ; 15 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.090 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; -; 6.218 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; -; 6.218 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; -; 6.218 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1295: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.842 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.238 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.266 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1296: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.796 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.230 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.259 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.263 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.171 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; -; 6.263 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1297: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; -; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.282 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1298: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.617 ; 80 ; 0.150 ; 0.746 ; -; Cell ; ; 14 ; 0.537 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.034 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.060 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.066 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.216 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.273 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1299: Setup slack is -0.667 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.667 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.223 ; 0.623 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~873|dataf ; -; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~873|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1300: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 81 ; 0.118 ; 0.734 ; -; Cell ; ; 14 ; 0.501 ; 15 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.268 ; 3.276 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.085 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.164 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.169 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.287 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.398 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.403 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.086 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.177 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.183 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.897 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.927 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.933 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.193 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.268 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1301: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.669 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.265 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.942 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.063 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.169 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.175 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.290 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.316 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.321 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.084 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.162 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.168 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.876 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.904 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.910 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.190 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.265 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1302: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 82 ; 0.110 ; 0.788 ; -; Cell ; ; 14 ; 0.470 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.147 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.253 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1303: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1304: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1305: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.130 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.132 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.130 ; 3.132 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; -; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1306: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.506 ; 76 ; 0.118 ; 0.755 ; -; Cell ; ; 14 ; 0.650 ; 20 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.274 ; 3.282 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.994 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.021 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.027 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.198 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.274 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1307: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.845 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.530 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.226 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1308: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.861 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.241 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1309: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.829 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.255 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; -; 6.281 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1310: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.358 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.387 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.391 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.235 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.264 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1311: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.450 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.248 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.276 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1312: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.249 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1313: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.179 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.266 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1314: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.797 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.456 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.485 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.490 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.237 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1315: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.233 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1316: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.329 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.460 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.492 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.497 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.221 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1317: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.230 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1318: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.454 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.483 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.488 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.184 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1319: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.839 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.220 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1320: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.230 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1321: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.822 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.217 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1322: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.745 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.442 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.471 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.476 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.182 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.261 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1323: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.862 ; 88 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.478 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.504 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.510 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.242 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.268 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1324: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.239 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.266 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1325: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+---------------------------------------------+ -; Path Summary ; -+--------------------+------------------------+ -; Property ; Value ; -+--------------------+------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.604 ; 83 ; 0.163 ; 1.398 ; -; Cell ; ; 10 ; 0.412 ; 13 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 4.653 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; -; 4.733 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.738 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.136 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1326: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.058 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.060 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.058 ; 3.060 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; -; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1327: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.058 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.060 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.058 ; 3.060 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; -; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1328: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.058 ; -; Data Required Time ; 5.392 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.060 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.058 ; 3.060 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; -; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1329: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.385 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.270 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1330: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.805 ; 86 ; 0.106 ; 1.302 ; -; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.153 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.272 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1331: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.786 ; 85 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.359 ; 11 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.265 ; 3.267 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.148 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.265 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1332: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.402 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.076 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.409 ; 78 ; 0.118 ; 0.829 ; -; Cell ; ; 10 ; 0.541 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.068 ; 3.076 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.068 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1333: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 80 ; 0.150 ; 0.746 ; -; Cell ; ; 14 ; 0.521 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.272 ; 3.280 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.033 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.059 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.065 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.215 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.272 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1334: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.735 ; 84 ; 0.106 ; 1.205 ; -; Cell ; ; 12 ; 0.398 ; 12 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.133 ; 1.205 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~111|datab ; -; 6.252 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~111|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1335: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.221 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1007|dataf ; -; 6.249 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1007|combout ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15]|d ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1336: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.810 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 12 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[10] ; -; 6.239 ; 0.640 ; RR ; IC ; 1 ; LABCELL_X95_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~888|dataf ; -; 6.266 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~888|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y145_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1337: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.547 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.242 ; 0.695 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~836|dataf ; -; 6.270 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~836|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1338: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.241 ; 0.679 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~580|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~580|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y152_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1339: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|warp_num[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.657 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.219 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.126 ; 0.711 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N9 ; High Speed ; vx_d_e_reg|i602~2|datac ; -; 6.219 ; 0.093 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N9 ; High Speed ; vx_d_e_reg|i602~2|combout ; -; 6.219 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2]|d ; -; 6.219 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N10 ; ; vx_d_e_reg|warp_num[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1340: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.033 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.239 ; 0.746 ; FF ; IC ; 1 ; MLABCELL_X105_Y157_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~907|dataf ; -; 6.266 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y157_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~907|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; -; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.165 ; ; uTsu ; 1 ; FF_X105_Y157_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1341: Setup slack is -0.666 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.666 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.240 ; 0.747 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~906|dataf ; -; 6.266 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X107_Y157_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~906|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1342: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[3] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.289 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.761 ; 84 ; 0.114 ; 0.775 ; -; Cell ; ; 16 ; 0.407 ; 12 ; 0.000 ; 0.081 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; -; 6.278 ; 3.289 ; ; ; ; ; ; data path ; -; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; -; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; -; 3.863 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|dataf ; -; 3.891 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; -; 3.897 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; -; 4.338 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; -; 4.419 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; -; 4.424 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; -; 4.779 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; -; 4.807 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; -; 4.813 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; -; 5.076 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; -; 5.135 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; -; 5.141 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; -; 5.264 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; -; 5.327 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.331 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.106 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.133 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.138 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.252 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.278 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1343: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.215 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.319 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.213 ; 3.215 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.186 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.213 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1344: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.177 ; 0.692 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; -; 6.269 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1345: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.694 ; 82 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.265 ; 3.267 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.173 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.265 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1346: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.358 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.436 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; -; 6.226 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1347: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.236 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1348: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.243 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.270 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1349: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.360 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.440 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.218 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.246 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1350: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+--------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+-----------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.877 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.239 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; -; 6.266 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1351: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; -; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.269 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1352: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.118 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.280 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1353: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.827 ; 87 ; 0.110 ; 1.378 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.229 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.259 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1354: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.068 ; -; Data Required Time ; 5.403 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.076 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.409 ; 78 ; 0.118 ; 0.829 ; -; Cell ; ; 10 ; 0.541 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.068 ; 3.076 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.068 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1355: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.616 ; 80 ; 0.147 ; 0.748 ; -; Cell ; ; 14 ; 0.540 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.036 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.062 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.068 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.215 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.275 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1356: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.617 ; 80 ; 0.150 ; 0.746 ; -; Cell ; ; 14 ; 0.537 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.034 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.060 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.066 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.216 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.273 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1357: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.839 ; 87 ; 0.106 ; 1.296 ; -; Cell ; ; 12 ; 0.306 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.237 ; 1.296 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|dataf ; -; 6.264 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1358: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.240 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~711|dataf ; -; 6.269 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~711|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1359: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.046 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.235 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X94_Y160_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~749|dataf ; -; 6.263 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y160_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~749|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13]|clk ; -; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; -; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.176 ; ; uTsu ; 1 ; FF_X94_Y160_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1360: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.187 ; 0.625 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~577|datad ; -; 6.279 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X107_Y153_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~577|combout ; -; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1]|d ; -; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y153_N49 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1361: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.220 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.222 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.624 ; 81 ; 0.192 ; 0.903 ; -; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.220 ; 3.222 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.192 ; 0.903 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.220 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1362: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[0] ; -; To Node ; vx_e_m_reg|alu_result[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.167 ; -; Data Required Time ; 5.502 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.526 ; 78 ; 0.132 ; 0.955 ; -; Cell ; ; 14 ; 0.467 ; 15 ; 0.000 ; 0.124 ; -; uTco ; ; 1 ; 0.227 ; 7 ; 0.227 ; 0.227 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 6.167 ; 3.220 ; ; ; ; ; ; data path ; -; 3.174 ; 0.227 ; FF ; uTco ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0]|q ; -; 3.221 ; 0.047 ; FF ; CELL ; 12 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]~la_lab/laboutb[1] ; -; 4.176 ; 0.955 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|dataa ; -; 4.300 ; 0.124 ; FR ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; -; 4.305 ; 0.005 ; RR ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; -; 4.437 ; 0.132 ; RR ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; -; 4.510 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.514 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.729 ; 0.215 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.792 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.796 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.244 ; 0.448 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.272 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.278 ; 0.006 ; RR ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.413 ; 0.135 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; -; 5.439 ; 0.026 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; -; 5.444 ; 0.005 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; -; 6.085 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; -; 6.167 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; -; 6.167 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; -; 6.167 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.502 ; 0.167 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1363: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.234 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X95_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~979|dataf ; -; 6.264 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X95_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~979|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y144_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1364: Setup slack is -0.665 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.665 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.053 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.216 ; 0.674 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~968|dataf ; -; 6.244 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~968|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8]|clk ; -; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; -; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.164 ; ; uTsu ; 1 ; FF_X89_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1365: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.212 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.641 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.212 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.184 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.212 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1366: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.642 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.213 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.185 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.213 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1367: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.671 ; 81 ; 0.128 ; 0.755 ; -; Cell ; ; 14 ; 0.482 ; 15 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.270 ; 3.278 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.990 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.017 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.023 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.194 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.270 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1368: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.046 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.223 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; -; 6.251 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; -; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1369: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.284 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.750 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.412 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.282 ; 3.284 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.450 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.189 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.282 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1370: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.281 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.283 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.281 ; 3.283 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.253 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.281 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1371: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.246 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.274 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1372: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.442 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.473 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.247 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.275 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1373: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.177 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.264 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1374: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.454 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.483 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.488 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.235 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1375: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.231 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.258 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1376: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.216 ; -; Data Required Time ; 5.552 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.218 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.631 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.466 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.216 ; 3.218 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.090 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; -; 6.216 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; -; 6.216 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; -; 6.216 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1377: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.171 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.263 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1378: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.850 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.420 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.447 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.453 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.232 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1379: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.793 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.364 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.450 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.190 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.277 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1380: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.176 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.258 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1381: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.631 ; 80 ; 0.147 ; 0.748 ; -; Cell ; ; 14 ; 0.524 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.274 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.035 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.061 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.067 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.214 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.274 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1382: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 80 ; 0.150 ; 0.746 ; -; Cell ; ; 14 ; 0.521 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.272 ; 3.280 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.033 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.059 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.065 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.215 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.272 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1383: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.633 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.252 ; 3.260 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.224 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1384: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.633 ; 81 ; 0.138 ; 0.722 ; -; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.252 ; 3.260 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.224 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1385: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.433 ; 0.005 ; FF ; CELL ; 18 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[7] ; -; 6.227 ; 0.794 ; FF ; IC ; 1 ; MLABCELL_X98_Y164_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~518|dataf ; -; 6.256 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X98_Y164_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~518|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y164_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1386: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.735 ; 84 ; 0.106 ; 1.205 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.133 ; 1.205 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~15|datab ; -; 6.250 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~15|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15]|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1387: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.440 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N28 ; ; vx_d_e_reg|PC_next_out[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1388: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.802 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.544 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[11] ; -; 6.236 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~686|dataf ; -; 6.263 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~686|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1389: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.440 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N16 ; ; vx_d_e_reg|PC_next_out[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1390: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|rs1[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.563 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.682 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.426 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.227 ; 3.229 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.151 ; 0.736 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N51 ; High Speed ; vx_d_e_reg|i316~3|datad ; -; 6.227 ; 0.076 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N51 ; High Speed ; vx_d_e_reg|i316~3|combout ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3]|d ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.563 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y155_N53 ; ; vx_d_e_reg|rs1[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1391: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.440 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N10 ; ; vx_d_e_reg|PC_next_out[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1392: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.219 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.639 ; 82 ; 0.192 ; 0.903 ; -; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.219 ; 3.227 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.191 ; 0.903 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.219 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1393: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.218 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.622 ; 81 ; 0.192 ; 0.901 ; -; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.218 ; 3.220 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.190 ; 0.901 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.218 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1394: Setup slack is -0.664 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.664 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.684 ; 82 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.094 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.166 ; 0.674 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~863|datac ; -; 6.260 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X98_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~863|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1395: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.210 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.218 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.210 ; 3.218 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.182 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.210 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.210 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.210 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1396: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[6] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.736 ; 84 ; 0.119 ; 1.072 ; -; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6]|clk ; -; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6] ; -; 6.261 ; 3.268 ; ; ; ; ; ; data path ; -; 3.114 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y160_N26 ; ; vx_csr_handler|decode_csr_address[6]|q ; -; 3.183 ; 0.069 ; RR ; CELL ; 326 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6]~la_lab/laboutt[17] ; -; 4.255 ; 1.072 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189|datae ; -; 4.328 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189|combout ; -; 4.332 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189~la_lab/laboutt[8] ; -; 4.451 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datac ; -; 4.535 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; -; 4.540 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; -; 5.064 ; 0.524 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; -; 5.090 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.094 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.218 ; 0.124 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.302 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.306 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.081 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.108 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.113 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.235 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.261 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1397: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.177 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; -; 6.264 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1398: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.741 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.170 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; -; 6.263 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1399: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.175 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.122 ; ; ; ; ; ; -; Data Delay ; 3.177 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.695 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.360 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.175 ; 3.177 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.148 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|dataf ; -; 6.175 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|combout ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|d ; -; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; -; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N22 ; ; vx_d_e_reg|csr_address[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1400: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.235 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.261 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1401: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.817 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.234 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.262 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1402: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.203 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.235 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.177 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.259 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1403: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.748 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.393 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.470 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.475 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.232 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1404: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.275 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.277 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.867 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.275 ; 3.277 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.249 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.275 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1405: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.226 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1406: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.219 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; -; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1407: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.058 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.060 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.058 ; 3.060 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; -; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1408: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.058 ; -; Data Required Time ; 5.395 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.089 ; ; ; ; ; ; -; Data Delay ; 3.060 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.058 ; 3.060 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; -; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; -; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; -; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1409: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.825 ; 87 ; 0.114 ; 1.366 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.230 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.258 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1410: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.267 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1411: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[23] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.459 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.459 ; 0.016 ; ; uTsu ; 1 ; FF_X72_Y160_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[23] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1412: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.239 ; 0.703 ; FF ; IC ; 1 ; LABCELL_X108_Y151_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~729|dataf ; -; 6.268 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X108_Y151_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~729|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.166 ; ; uTsu ; 1 ; FF_X108_Y151_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1413: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.277 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.279 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.277 ; 3.279 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.249 ; 0.694 ; RR ; IC ; 1 ; MLABCELL_X96_Y144_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~730|dataf ; -; 6.277 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X96_Y144_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~730|combout ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26]|d ; -; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y144_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1414: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.546 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; -; 6.235 ; 0.689 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~790|dataf ; -; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y144_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~790|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1415: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.283 ; -; Data Required Time ; 5.620 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.011 ; ; ; ; ; ; -; Data Delay ; 3.285 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.283 ; 3.285 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.255 ; 0.732 ; FF ; IC ; 1 ; LABCELL_X108_Y155_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~746|dataf ; -; 6.283 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X108_Y155_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~746|combout ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10]|d ; -; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.487 ; 2.987 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; -; 5.487 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.457 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.620 ; 0.163 ; ; uTsu ; 1 ; FF_X108_Y155_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1416: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.217 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.637 ; 82 ; 0.192 ; 0.901 ; -; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.217 ; 3.225 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.189 ; 0.901 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.217 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1417: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.459 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.459 ; 0.016 ; ; uTsu ; 1 ; FF_X72_Y160_N16 ; ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1418: Setup slack is -0.663 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.663 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.743 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.238 ; 0.767 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~878|dataf ; -; 6.263 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X101_Y161_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~878|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X101_Y161_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1419: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.673 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.249 ; 3.257 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.455 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.481 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.487 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.175 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.249 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1420: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.683 ; 82 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.264 ; 3.272 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.893 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.923 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.929 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.189 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.264 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1421: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.671 ; 81 ; 0.128 ; 0.755 ; -; Cell ; ; 14 ; 0.482 ; 15 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.270 ; 3.278 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.990 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.017 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.023 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.194 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.270 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1422: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.220 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; -; 6.248 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1423: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.736 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.412 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.500 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.504 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.176 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.268 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1424: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.280 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.282 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.280 ; 3.282 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.187 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.280 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1425: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.279 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.281 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.279 ; 3.281 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.251 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.279 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1426: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.171 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.263 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1427: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.572 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.364 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.309 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.389 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.393 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.207 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; -; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1428: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.466 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.217 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; -; 6.245 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1429: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.768 ; 85 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.377 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.408 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.413 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; -; 6.133 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; -; 6.263 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1430: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.106 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.108 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.106 ; 3.108 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.106 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|sclr ; -; 6.106 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1431: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|a_reg_data[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.106 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.108 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.106 ; 3.108 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.106 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|sclr ; -; 6.106 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N40 ; ; vx_d_e_reg|a_reg_data[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1432: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.827 ; 87 ; 0.110 ; 1.378 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.229 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.259 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1433: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.064 ; -; Data Required Time ; 5.402 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.072 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.574 ; 84 ; 0.128 ; 0.829 ; -; Cell ; ; 10 ; 0.373 ; 12 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.064 ; 3.072 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.064 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.064 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1434: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.835 ; 87 ; 0.106 ; 1.292 ; -; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.233 ; 1.292 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|dataf ; -; 6.261 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1435: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y160_N20 ; ; vx_fetch|VX_Warp_zero|real_PC[28] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1436: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.033 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.237 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X97_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~916|dataf ; -; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~916|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; -; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y145_N52 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1437: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.757 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.186 ; 0.669 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~569|datad ; -; 6.268 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X108_Y151_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~569|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y151_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1438: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N20 ; ; vx_d_e_reg|PC_next_out[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1439: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.225 ; -; Data Required Time ; 5.563 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.683 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.423 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.225 ; 3.227 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.152 ; 0.737 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N42 ; High Speed ; vx_d_e_reg|i531~1|datae ; -; 6.225 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N42 ; High Speed ; vx_d_e_reg|i531~1|combout ; -; 6.225 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1]|d ; -; 6.225 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.563 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y155_N43 ; ; vx_d_e_reg|csr_mask[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1440: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N8 ; ; vx_d_e_reg|PC_next_out[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1441: Setup slack is -0.662 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.662 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N2 ; ; vx_d_e_reg|PC_next_out[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1442: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.162 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; -; 6.244 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1443: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.229 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; -; 6.255 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1444: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.560 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; -; 6.226 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; -; 6.254 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1445: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.221 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1446: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.220 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.248 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1447: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.220 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.248 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1448: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.817 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.233 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.259 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1449: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.201 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.228 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.233 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.175 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.257 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1450: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.236 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1451: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.240 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.267 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1452: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.215 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1453: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.409 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.436 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.442 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.232 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; -; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1454: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.473 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.499 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.505 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.237 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1455: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.844 ; 87 ; 0.104 ; 1.366 ; -; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.228 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.256 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1456: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; -; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.259 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1457: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.786 ; 85 ; 0.104 ; 1.302 ; -; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.148 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.267 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1458: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.064 ; -; Data Required Time ; 5.403 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.072 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.574 ; 84 ; 0.128 ; 0.829 ; -; Cell ; ; 10 ; 0.373 ; 12 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.064 ; 3.072 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.064 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.064 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1459: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.727 ; 83 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.179 ; 0.644 ; FF ; IC ; 1 ; MLABCELL_X96_Y142_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~662|datac ; -; 6.266 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X96_Y142_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~662|combout ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22]|d ; -; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.175 ; ; uTsu ; 1 ; FF_X96_Y142_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1460: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X72_Y160_N2 ; ; vx_fetch|VX_Warp_zero|real_PC[22] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1461: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.438 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.442 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.216 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|dataf ; -; 6.243 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1462: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 12 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[10] ; -; 6.232 ; 0.633 ; RR ; IC ; 1 ; LABCELL_X95_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~895|dataf ; -; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~895|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.164 ; ; uTsu ; 1 ; FF_X95_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1463: Setup slack is -0.661 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.661 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.169 ; 0.570 ; RR ; IC ; 1 ; LABCELL_X97_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~512|datac ; -; 6.251 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X97_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~512|combout ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0]|d ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1464: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.208 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.574 ; 80 ; 0.127 ; 0.668 ; -; Cell ; ; 14 ; 0.515 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.208 ; 3.210 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.181 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.208 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1465: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.208 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.626 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.208 ; 3.210 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.180 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.208 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1466: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.209 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.211 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.627 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.209 ; 3.211 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.181 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.209 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.209 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.209 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1467: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.657 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.483 ; 15 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.870 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.898 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.904 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.184 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.259 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1468: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.644 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.497 ; 15 ; 0.000 ; 0.113 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.259 ; 3.267 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.870 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.898 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.904 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.184 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.259 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1469: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[4] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.161 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.213 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.575 ; 80 ; 0.109 ; 0.747 ; -; Cell ; ; 16 ; 0.516 ; 16 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4] ; -; 6.161 ; 3.213 ; ; ; ; ; ; data path ; -; 3.070 ; 0.122 ; FF ; uTco ; 1 ; FF_X79_Y153_N43 ; ; vx_d_e_reg|b_reg_data[4]|q ; -; 3.138 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]~la_lab/laboutb[8] ; -; 3.884 ; 0.746 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|dataf ; -; 3.911 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|combout ; -; 3.915 ; 0.004 ; FF ; CELL ; 42 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18~la_lab/laboutb[2] ; -; 4.081 ; 0.166 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|datab ; -; 4.189 ; 0.108 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|combout ; -; 4.194 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27~la_lab/laboutt[5] ; -; 4.303 ; 0.109 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataa ; -; 4.430 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.434 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.651 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.726 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.730 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.163 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.190 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.196 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.353 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.381 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.133 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.161 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1470: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_mask[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.220 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; -; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1471: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|csr_mask[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.220 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; -; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1472: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.835 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.530 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.216 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; -; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1473: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.510 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.174 ; 0.664 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; -; 6.260 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1474: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.694 ; 82 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.265 ; 3.267 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.173 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; -; 6.265 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1475: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.807 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.358 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.387 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.391 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.235 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.264 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1476: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.227 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1477: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.823 ; 87 ; 0.119 ; 1.046 ; -; Cell ; ; 14 ; 0.299 ; 9 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.450 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.479 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.485 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.216 ; 0.731 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; -; 6.242 ; 0.026 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1478: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|rs1[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.226 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.726 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.224 ; 3.226 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.196 ; 0.843 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|dataf ; -; 6.224 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|combout ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|d ; -; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N2 ; ; vx_d_e_reg|rs1[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1479: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.678 ; 82 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.427 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.431 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.167 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.249 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1480: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.750 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.188 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.274 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1481: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.467 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.498 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.502 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.174 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.266 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1482: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.735 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.203 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.235 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.172 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.254 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1483: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.818 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.224 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; -; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1484: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.578 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.240 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.806 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.238 ; 3.240 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.211 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; -; 6.238 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1485: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|b_reg_data[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.215 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.119 ; 0.855 ; -; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.213 ; 3.215 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.185 ; 0.855 ; RR ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; -; 6.213 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1486: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.800 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.380 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.457 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.461 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.229 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1487: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.101 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.103 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.101 ; 3.103 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; -; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1488: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.101 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.103 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.101 ; 3.103 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; -; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1489: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.101 ; -; Data Required Time ; 5.441 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.103 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.101 ; 3.103 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; -; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1490: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.770 ; 85 ; 0.116 ; 1.302 ; -; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.142 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; -; 6.259 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1491: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.413 ; 0.485 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|datad ; -; 5.489 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|combout ; -; 5.493 ; 0.004 ; RR ; CELL ; 15 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17~la_lab/laboutb[2] ; -; 6.225 ; 0.732 ; RR ; IC ; 1 ; LABCELL_X95_Y142_N45 ; Mixed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~566|dataf ; -; 6.253 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y142_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~566|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y142_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1492: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.227 ; 0.676 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~604|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~604|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1493: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N50 ; ; vx_d_e_reg|PC_next_out[18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1494: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N38 ; ; vx_d_e_reg|PC_next_out[14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1495: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.444 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N32 ; ; vx_d_e_reg|PC_next_out[12] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1496: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.190 ; 0.264 ; RR ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; -; 5.218 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; -; 5.224 ; 0.006 ; FF ; CELL ; 3 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[0] ; -; 6.244 ; 1.020 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~354|dataf ; -; 6.273 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X101_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~354|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1497: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.111 ; ; ; ; ; ; -; Data Delay ; 2.219 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.834 ; 83 ; 0.422 ; 0.843 ; -; Cell ; ; 8 ; 0.252 ; 11 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|clk ; -; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; -; 6.289 ; 2.219 ; ; ; ; ; ; data path ; -; 4.203 ; 0.133 ; RR ; uTco ; 1 ; FF_X104_Y149_N40 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|q ; -; 4.264 ; 0.061 ; RR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.833 ; 0.569 ; RR ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataa ; -; 4.965 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 4.969 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.812 ; 0.843 ; RR ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.836 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.841 ; 0.005 ; RR ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.263 ; 0.422 ; RR ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.289 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1498: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.214 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.216 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.618 ; 81 ; 0.192 ; 0.897 ; -; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.214 ; 3.216 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.186 ; 0.897 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.214 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.214 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.214 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1499: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.629 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.111 ; ; ; ; ; ; -; Data Delay ; 2.219 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.834 ; 83 ; 0.422 ; 0.843 ; -; Cell ; ; 8 ; 0.252 ; 11 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|clk ; -; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; -; 6.289 ; 2.219 ; ; ; ; ; ; data path ; -; 4.203 ; 0.133 ; RR ; uTco ; 1 ; FF_X104_Y149_N40 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|q ; -; 4.264 ; 0.061 ; RR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; -; 4.833 ; 0.569 ; RR ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataa ; -; 4.965 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; -; 4.969 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; -; 5.812 ; 0.843 ; RR ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; -; 5.836 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; -; 5.841 ; 0.005 ; RR ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; -; 6.263 ; 0.422 ; RR ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; -; 6.289 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; -; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; -; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1500: Setup slack is -0.660 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.660 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.236 ; 0.744 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~839|dataf ; -; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~839|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1501: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.208 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.624 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.206 ; 3.208 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.178 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.206 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1502: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.699 ; 83 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.246 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.452 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.478 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.484 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.172 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.246 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1503: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.709 ; 83 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.433 ; 13 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.261 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.890 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.920 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.926 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.186 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.261 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1504: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.582 ; 79 ; 0.118 ; 0.714 ; -; Cell ; ; 14 ; 0.560 ; 17 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.078 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.157 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.162 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.280 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.391 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.396 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.079 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.170 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.890 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.920 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.926 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.186 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.261 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1505: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.230 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.258 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1506: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.863 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; -; 6.245 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; -; 6.271 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; -; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1507: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.235 ; 0.675 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; -; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1508: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_mask[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.223 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.725 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.223 ; 3.225 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.195 ; 0.842 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|dataf ; -; 6.223 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|combout ; -; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|d ; -; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N7 ; ; vx_d_e_reg|csr_mask[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1509: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.678 ; 82 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.427 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.431 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.167 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.249 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1510: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.477 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.481 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.232 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.258 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1511: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.215 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1512: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.218 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.246 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1513: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.218 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.246 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1514: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.386 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.413 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.418 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.166 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.258 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1515: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.448 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.227 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.255 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1516: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|a_reg_data[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.101 ; -; Data Required Time ; 5.442 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.103 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.101 ; 3.103 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; -; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1517: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.236 ; 0.693 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N0 ; Mixed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~693|dataf ; -; 6.263 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~693|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y147_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1518: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.181 ; 0.619 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|datad ; -; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1519: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.633 ; 82 ; 0.192 ; 0.897 ; -; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.213 ; 3.221 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.185 ; 0.897 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.213 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1520: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.438 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.442 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.216 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|dataf ; -; 6.243 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y164_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1521: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.181 ; 0.619 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|datad ; -; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1522: Setup slack is -0.659 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.274 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.659 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.276 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.094 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.274 ; 3.276 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.180 ; 0.639 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~962|datac ; -; 6.274 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~962|combout ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2]|d ; -; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1523: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[28] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.087 ; ; ; ; ; ; -; Data Delay ; 3.207 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.544 ; 79 ; 0.120 ; 0.813 ; -; Cell ; ; 16 ; 0.482 ; 15 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.181 ; 6 ; 0.181 ; 0.181 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; -; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; -; 6.159 ; 3.207 ; ; ; ; ; ; data path ; -; 3.133 ; 0.181 ; FF ; uTco ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28]|q ; -; 3.177 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]~la_lab/laboutb[14] ; -; 3.990 ; 0.813 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|dataf ; -; 4.017 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|combout ; -; 4.022 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41~la_lab/laboutb[11] ; -; 4.164 ; 0.142 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|datae ; -; 4.242 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|combout ; -; 4.248 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45~la_mlab/laboutb[16] ; -; 4.380 ; 0.132 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datac ; -; 4.466 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; -; 4.472 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; -; 4.592 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; -; 4.724 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.728 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.161 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.188 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.194 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.351 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.379 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.384 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.131 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.159 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1524: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.214 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.685 ; 84 ; 0.115 ; 0.734 ; -; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.206 ; 3.214 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.178 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.206 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1525: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.207 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.215 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.686 ; 84 ; 0.115 ; 0.734 ; -; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.207 ; 3.215 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.179 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.207 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1526: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.833 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.212 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; -; 6.240 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1527: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.276 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.278 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.276 ; 3.278 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.249 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; -; 6.276 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; -; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1528: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.843 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.224 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; -; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1529: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.213 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; -; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1530: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1531: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.522 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.218 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; -; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1532: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.803 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.233 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1533: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.247 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; -; 6.273 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1534: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|csr_address[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.170 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.122 ; ; ; ; ; ; -; Data Delay ; 3.172 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.689 ; 85 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.170 ; 3.172 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.142 ; 0.780 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|dataf ; -; 6.170 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|combout ; -; 6.170 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|d ; -; 6.170 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; -; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N11 ; ; vx_d_e_reg|csr_address[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1535: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.738 ; 84 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.413 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.445 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.477 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.481 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.179 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.271 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1536: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.697 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.425 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.429 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.165 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.247 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1537: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.186 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.272 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1538: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.201 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.228 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.233 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.170 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.252 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1539: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.244 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.270 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1540: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.271 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.273 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.375 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.271 ; 3.273 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.444 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.184 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; -; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; -; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1541: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.766 ; 85 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.170 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; -; 6.252 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1542: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.211 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.077 ; ; ; ; ; ; -; Data Delay ; 3.213 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.744 ; 85 ; 0.108 ; 0.876 ; -; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.211 ; 3.213 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.184 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; -; 6.211 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; -; 6.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; -; 6.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; -; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; -; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1543: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.353 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.380 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.384 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.150 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; -; 6.243 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1544: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[29] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.419 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.419 ; 0.014 ; ; uTsu ; 1 ; FF_X80_Y155_N22 ; ; vx_d_e_reg|PC_next_out[29] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1545: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.524 ; 78 ; 0.118 ; 0.944 ; -; Cell ; ; 12 ; 0.571 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.213 ; 3.221 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.184 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.213 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1546: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.213 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.221 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.523 ; 78 ; 0.118 ; 0.943 ; -; Cell ; ; 12 ; 0.572 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.213 ; 3.221 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.183 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.213 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1547: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.021 ; ; uTsu ; 1 ; FF_X72_Y160_N25 ; ; vx_fetch|VX_Warp_zero|real_PC[30] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1548: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.214 ; 0.646 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1009|dataf ; -; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1009|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1549: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.446 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.446 ; 0.060 ; ; uTsu ; 1 ; FF_X80_Y156_N25 ; ; vx_d_e_reg|PC_next_out[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1550: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; -; 6.232 ; 0.632 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~534|dataf ; -; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y144_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~534|combout ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22]|d ; -; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1551: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.212 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.220 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.647 ; 82 ; 0.142 ; 0.929 ; -; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.212 ; 3.220 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.183 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.212 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1552: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.159 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.087 ; ; ; ; ; ; -; Data Delay ; 3.207 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.451 ; 76 ; 0.120 ; 0.864 ; -; Cell ; ; 16 ; 0.574 ; 18 ; 0.000 ; 0.132 ; -; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 6.159 ; 3.207 ; ; ; ; ; ; data path ; -; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; -; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; -; 4.042 ; 0.864 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|dataf ; -; 4.069 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|combout ; -; 4.075 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22~la_mlab/laboutb[3] ; -; 4.196 ; 0.121 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datab ; -; 4.307 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; -; 4.313 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; -; 4.437 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; -; 4.527 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; -; 4.533 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; -; 4.653 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; -; 4.785 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.789 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.222 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.255 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.385 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; -; 5.412 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; -; 5.417 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; -; 6.076 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; -; 6.159 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; -; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1553: Setup slack is -0.658 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.658 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.229 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~826|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~826|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1554: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.204 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.212 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.683 ; 84 ; 0.115 ; 0.734 ; -; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.204 ; 3.212 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; -; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.176 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1555: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.711 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 14 ; 0.432 ; 13 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.021 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; -; 6.051 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; -; 6.057 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; -; 6.187 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; -; 6.263 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1556: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.853 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.260 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1557: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.510 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.170 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; -; 6.249 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1558: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.743 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.169 ; 0.692 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; -; 6.261 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1559: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.304 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.337 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.227 ; 0.890 ; RR ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1560: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.331 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.360 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.364 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.208 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.234 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1561: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.697 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.082 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.425 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.429 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.165 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.247 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1562: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.810 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.443 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.475 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.230 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.256 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1563: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.213 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1564: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.409 ; 13 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.168 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.197 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.201 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.166 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.257 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1565: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.768 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.455 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.484 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.490 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.209 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1566: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[16] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.536 ; 79 ; 0.111 ; 0.747 ; -; Cell ; ; 16 ; 0.491 ; 15 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -; 6.158 ; 3.210 ; ; ; ; ; ; data path ; -; 3.131 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16]|q ; -; 3.175 ; 0.044 ; FF ; CELL ; 3 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]~la_lab/laboutb[1] ; -; 3.900 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8|datad ; -; 3.974 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8|combout ; -; 3.978 ; 0.004 ; FF ; CELL ; 5 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8~la_lab/laboutt[10] ; -; 4.111 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5|dataf ; -; 4.137 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5|combout ; -; 4.142 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5~la_lab/laboutb[5] ; -; 4.372 ; 0.230 ; FF ; IC ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38|datab ; -; 4.480 ; 0.108 ; FF ; CELL ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38|combout ; -; 4.486 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38~la_mlab/laboutb[17] ; -; 4.597 ; 0.111 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datab ; -; 4.723 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.727 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.160 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.187 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.193 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.350 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.378 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.383 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.130 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.158 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1567: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.386 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.413 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.418 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.166 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.258 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1568: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.814 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.220 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; -; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1569: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[27] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.420 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.420 ; 0.015 ; ; uTsu ; 1 ; FF_X80_Y155_N16 ; ; vx_d_e_reg|PC_next_out[27] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1570: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; -; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.272 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1571: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; -; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.256 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1572: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; -; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.272 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1573: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.821 ; 87 ; 0.110 ; 1.372 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.223 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.253 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1574: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.617 ; 80 ; 0.138 ; 0.748 ; -; Cell ; ; 14 ; 0.533 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.267 ; 3.275 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.028 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; -; 6.054 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; -; 6.060 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; -; 6.207 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; -; 6.267 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; -; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1575: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N13 ; ; vx_fetch|VX_Warp_zero|real_PC[26] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1576: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N29 ; ; vx_fetch|VX_Warp_zero|real_PC[31] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1577: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.243 ; 0.542 ; RR ; IC ; 1 ; MLABCELL_X96_Y146_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~787|dataf ; -; 6.269 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X96_Y146_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~787|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.176 ; ; uTsu ; 1 ; FF_X96_Y146_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1578: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.447 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N23 ; ; vx_d_e_reg|PC_next_out[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1579: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.447 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N13 ; ; vx_d_e_reg|PC_next_out[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1580: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.447 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N5 ; ; vx_d_e_reg|PC_next_out[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1581: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N19 ; ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1582: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.059 ; -; Data Required Time ; 5.402 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.067 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.547 ; 83 ; 0.170 ; 0.829 ; -; Cell ; ; 10 ; 0.393 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.059 ; 3.067 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.947 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.117 ; 0.170 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.201 ; 0.084 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.206 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.446 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.451 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.134 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.225 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.230 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.059 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.059 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1583: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[9] ; -; To Node ; vx_e_m_reg|alu_result[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.158 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.211 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.480 ; 77 ; 0.130 ; 0.774 ; -; Cell ; ; 16 ; 0.497 ; 15 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; -; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; -; 6.158 ; 3.211 ; ; ; ; ; ; data path ; -; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; -; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; -; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; -; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; -; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; -; 4.234 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|datad ; -; 4.323 ; 0.089 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|combout ; -; 4.329 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32~la_mlab/laboutt[1] ; -; 4.460 ; 0.131 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataf ; -; 4.488 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.492 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.709 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.784 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.788 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.221 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.254 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.384 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; -; 5.411 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; -; 5.416 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; -; 6.075 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; -; 6.158 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; -; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1584: Setup slack is -0.657 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.657 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.220 ; 0.707 ; RR ; IC ; 1 ; MLABCELL_X98_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~902|dataf ; -; 6.248 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X98_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~902|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1585: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.637 ; 81 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.242 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.436 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.462 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.468 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.180 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.242 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1586: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.204 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.582 ; 81 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.204 ; 3.206 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; -; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.176 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1587: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.205 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.207 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.583 ; 81 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.205 ; 3.207 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; -; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.177 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.205 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1588: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.205 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.060 ; ; ; ; ; ; -; Data Delay ; 3.228 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.633 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.205 ; 3.228 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; -; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.177 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.205 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1589: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.204 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.060 ; ; ; ; ; ; -; Data Delay ; 3.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.204 ; 3.227 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; -; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.176 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1590: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.113 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.115 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.113 ; 3.115 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; -; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1591: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.278 ; -; Data Required Time ; 5.622 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.280 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.871 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.278 ; 3.280 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.251 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; -; 6.278 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; -; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1592: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.375 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.404 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.408 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.226 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.255 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1593: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.757 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.443 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.475 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.177 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.269 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1594: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.748 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.384 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.460 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.464 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.230 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1595: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.161 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.125 ; ; ; ; ; ; -; Data Delay ; 3.163 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.646 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.396 ; 13 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.161 ; 3.163 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.336 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.088 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; -; 6.161 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1596: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|b_reg_data[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.204 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.618 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.467 ; 15 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.204 ; 3.206 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; -; 6.204 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; -; 6.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; -; 6.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1597: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.351 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.287 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.317 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.321 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.174 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.260 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1598: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.775 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.210 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.237 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1599: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.210 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.212 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.210 ; 3.212 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.182 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.210 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1600: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.421 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.421 ; 0.016 ; ; uTsu ; 1 ; FF_X80_Y155_N14 ; ; vx_d_e_reg|PC_next_out[26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1601: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_f_d_reg|curr_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.121 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.123 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.726 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.121 ; 3.123 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.121 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; -; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1602: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_f_d_reg|curr_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.121 ; -; Data Required Time ; 5.465 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.123 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.726 ; 87 ; 0.119 ; 1.297 ; -; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.121 ; 3.123 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.121 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; -; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1603: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.210 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.218 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.520 ; 78 ; 0.118 ; 0.940 ; -; Cell ; ; 12 ; 0.572 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.210 ; 3.218 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.180 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.210 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1604: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.262 ; 3.270 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.982 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.009 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.015 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.186 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.262 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1605: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.604 ; 80 ; 0.123 ; 0.760 ; -; Cell ; ; 14 ; 0.542 ; 17 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.265 ; 3.267 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.048 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.077 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.083 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.206 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.265 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1606: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.466 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N11 ; ; vx_fetch|VX_Warp_zero|real_PC[25] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1607: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[27] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.466 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N17 ; ; vx_fetch|VX_Warp_zero|real_PC[27] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1608: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[29] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.466 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N23 ; ; vx_fetch|VX_Warp_zero|real_PC[29] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1609: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.242 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~722|dataf ; -; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~722|combout ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18]|d ; -; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y146_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1610: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.122 ; -; Data Required Time ; 5.466 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.124 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.122 ; 3.124 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; -; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24]|sload ; -; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[24] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1611: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.448 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.448 ; 0.062 ; ; uTsu ; 1 ; FF_X80_Y156_N43 ; ; vx_d_e_reg|PC_next_out[16] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1612: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.241 ; 0.673 ; RR ; IC ; 1 ; LABCELL_X104_Y148_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1010|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y148_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1010|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y148_N14 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1613: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.796 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.227 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X94_Y145_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~984|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y145_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~984|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y145_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1614: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.074 ; -; Data Required Time ; 5.418 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.079 ; ; ; ; ; ; -; Data Delay ; 3.076 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.507 ; 82 ; 0.192 ; 0.786 ; -; Cell ; ; 10 ; 0.448 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.074 ; 3.076 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.074 ; 0.786 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.074 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.418 ; 0.029 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1615: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.059 ; -; Data Required Time ; 5.403 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.067 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.547 ; 83 ; 0.170 ; 0.829 ; -; Cell ; ; 10 ; 0.393 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.059 ; 3.067 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.947 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.117 ; 0.170 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.201 ; 0.084 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.206 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.446 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.451 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.134 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.225 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.230 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.059 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.059 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1616: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.074 ; -; Data Required Time ; 5.418 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.079 ; ; ; ; ; ; -; Data Delay ; 3.076 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.507 ; 82 ; 0.192 ; 0.786 ; -; Cell ; ; 10 ; 0.448 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.074 ; 3.076 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.074 ; 0.786 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.074 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.418 ; 0.029 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1617: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.215 ; 0.673 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~966|dataf ; -; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~966|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.160 ; ; uTsu ; 1 ; FF_X97_Y164_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1618: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.668 ; 82 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.150 ; 0.656 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~936|datac ; -; 6.242 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~936|combout ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8]|d ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.167 ; ; uTsu ; 1 ; FF_X94_Y165_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1619: Setup slack is -0.656 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.656 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.222 ; 0.727 ; RR ; IC ; 1 ; MLABCELL_X90_Y143_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~892|dataf ; -; 6.248 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y143_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~892|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y143_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1620: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.202 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.204 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.580 ; 81 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.202 ; 3.204 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; -; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.174 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1621: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.202 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.060 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.630 ; 82 ; 0.192 ; 0.657 ; -; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.202 ; 3.225 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; -; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.174 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1622: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.366 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.444 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.449 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; -; 6.217 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; -; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1623: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.169 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; -; 6.256 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1624: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.227 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1625: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.329 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.358 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.362 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.206 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.232 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1626: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.449 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.481 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.486 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.210 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1627: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.219 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1628: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.166 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.195 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.199 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.164 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.255 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1629: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.453 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.482 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.488 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.207 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1630: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.736 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.443 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.472 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.477 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.173 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.260 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1631: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.375 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.452 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.456 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.224 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1632: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.209 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; -; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1633: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 87 ; 0.116 ; 1.094 ; -; Cell ; ; 14 ; 0.311 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.467 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.493 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.499 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.231 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; -; 6.257 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1634: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.241 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.239 ; 3.241 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.211 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; -; 6.239 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1635: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.210 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.212 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.910 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.210 ; 3.212 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.182 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; -; 6.210 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; -; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1636: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.779 ; 86 ; 0.114 ; 1.228 ; -; Cell ; ; 12 ; 0.345 ; 11 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.124 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; -; 6.244 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1637: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; -; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.259 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1638: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.770 ; 85 ; 0.116 ; 1.302 ; -; Cell ; ; 12 ; 0.372 ; 11 ; 0.000 ; 0.119 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.142 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; -; 6.261 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1639: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.619 ; 80 ; 0.123 ; 0.760 ; -; Cell ; ; 14 ; 0.526 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.264 ; 3.272 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.047 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.076 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.082 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.205 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.264 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1640: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.449 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.449 ; 0.063 ; ; uTsu ; 1 ; FF_X80_Y156_N47 ; ; vx_d_e_reg|PC_next_out[17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1641: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.778 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.228 ; 0.705 ; FF ; IC ; 1 ; LABCELL_X102_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~738|dataf ; -; 6.256 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X102_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~738|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1642: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.273 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.273 ; 3.275 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.432 ; 0.005 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[7] ; -; 6.180 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X103_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~658|datac ; -; 6.273 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~658|combout ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18]|d ; -; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y145_N52 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1643: Setup slack is -0.655 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.655 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.229 ; 0.737 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|dataf ; -; 6.255 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1644: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[1] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.537 ; 78 ; 0.118 ; 0.708 ; -; Cell ; ; 14 ; 0.596 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; -; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; -; 3.849 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.855 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.007 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.137 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.142 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.260 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.371 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.376 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.059 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.150 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.156 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.864 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.892 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.898 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.178 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.253 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1645: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.482 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1646: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.482 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1647: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.482 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1648: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.208 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.076 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.208 ; 3.210 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.345 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.375 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.379 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.181 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; -; 6.208 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; -; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; -; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1649: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.834 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.214 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; -; 6.242 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1650: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.733 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.212 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; -; 6.240 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1651: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.208 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.773 ; 86 ; 0.108 ; 0.908 ; -; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.208 ; 3.210 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.180 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; -; 6.208 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; -; 6.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; -; 6.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1652: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.209 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.217 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.689 ; 84 ; 0.128 ; 0.944 ; -; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.209 ; 3.217 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.180 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.209 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1653: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.209 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.217 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.688 ; 84 ; 0.128 ; 0.943 ; -; Cell ; ; 12 ; 0.404 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.209 ; 3.217 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.179 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.209 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1654: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.664 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.262 ; 3.270 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.982 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 6.009 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.015 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.186 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.262 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; -; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1655: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; -; Cell ; ; 12 ; 0.401 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; -; 6.269 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1656: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.056 ; -; Data Required Time ; 5.402 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.064 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.567 ; 84 ; 0.115 ; 0.829 ; -; Cell ; ; 10 ; 0.372 ; 12 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.056 ; 3.064 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.056 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; -; 6.056 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1657: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[7] ; -; To Node ; vx_e_m_reg|alu_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.013 ; ; ; ; ; ; -; Data Delay ; 3.275 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.703 ; 83 ; 0.113 ; 1.025 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; -; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; -; 6.268 ; 3.275 ; ; ; ; ; ; data path ; -; 3.116 ; 0.123 ; RR ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; -; 3.212 ; 0.096 ; RR ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; -; 4.237 ; 1.025 ; RR ; IC ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|datac ; -; 4.330 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|combout ; -; 4.336 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174~la_mlab/laboutt[3] ; -; 4.481 ; 0.145 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datae ; -; 4.556 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; -; 4.561 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; -; 5.077 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; -; 5.103 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.107 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.234 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.321 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.098 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.124 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.242 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; -; 6.268 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1658: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.450 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N59 ; ; vx_d_e_reg|PC_next_out[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1659: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.266 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.268 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.266 ; 3.268 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; -; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; -; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; -; 6.237 ; 0.805 ; FF ; IC ; 1 ; MLABCELL_X96_Y163_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~517|dataf ; -; 6.266 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X96_Y163_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~517|combout ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5]|d ; -; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y163_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1660: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.450 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N55 ; ; vx_d_e_reg|PC_next_out[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1661: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.450 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N53 ; ; vx_d_e_reg|PC_next_out[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1662: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.450 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N41 ; ; vx_d_e_reg|PC_next_out[15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1663: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|PC_next_out[13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.104 ; -; Data Required Time ; 5.450 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.106 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.104 ; 3.106 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13]|sclr ; -; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13]|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13] ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N35 ; ; vx_d_e_reg|PC_next_out[13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1664: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.289 ; -; Data Required Time ; 5.635 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.091 ; ; ; ; ; ; -; Data Delay ; 2.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.859 ; 83 ; 0.392 ; 0.786 ; -; Cell ; ; 8 ; 0.243 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|clk ; -; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; -; 6.289 ; 2.234 ; ; ; ; ; ; data path ; -; 4.187 ; 0.132 ; FF ; uTco ; 1 ; FF_X90_Y148_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|q ; -; 4.230 ; 0.043 ; FF ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]~la_mlab/laboutb[17] ; -; 4.911 ; 0.681 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datad ; -; 4.989 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 4.994 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.780 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.806 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.811 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.203 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; -; 6.289 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; -; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; -; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1665: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.288 ; -; Data Required Time ; 5.634 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.095 ; ; ; ; ; ; -; Data Delay ; 2.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.864 ; 84 ; 0.370 ; 0.786 ; -; Cell ; ; 8 ; 0.226 ; 10 ; 0.000 ; 0.069 ; -; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; -; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; -; 6.288 ; 2.229 ; ; ; ; ; ; data path ; -; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; -; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; -; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; -; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.229 ; 0.370 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~16|datae ; -; 6.288 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~16|combout ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19]|d ; -; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X74_Y159_N14 ; ; vx_fetch|VX_Warp_three|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1666: Setup slack is -0.654 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[14] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.295 ; -; Data Required Time ; 5.641 ; -; Slack ; -0.654 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.095 ; ; ; ; ; ; -; Data Delay ; 2.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 76 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.845 ; 83 ; 0.366 ; 0.887 ; -; Cell ; ; 8 ; 0.257 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.060 ; 3.060 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.060 ; 2.317 ; FF ; IC ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]|clk ; -; 4.060 ; 0.000 ; FR ; CELL ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; -; 6.295 ; 2.235 ; ; ; ; ; ; data path ; -; 4.193 ; 0.133 ; FF ; uTco ; 1 ; FF_X98_Y162_N8 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]|q ; -; 4.236 ; 0.043 ; FF ; CELL ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]~la_mlab/laboutt[5] ; -; 5.123 ; 0.887 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33|datad ; -; 5.208 ; 0.085 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33|combout ; -; 5.212 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33~la_lab/laboutb[14] ; -; 5.804 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34|dataf ; -; 5.832 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34|combout ; -; 5.837 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34~la_lab/laboutb[15] ; -; 6.203 ; 0.366 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N42 ; High Speed ; vx_fetch|VX_Warp_one|i199~9|datad ; -; 6.295 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N42 ; High Speed ; vx_fetch|VX_Warp_one|i199~9|combout ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14]|d ; -; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14] ; -; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.641 ; 0.206 ; ; uTsu ; 1 ; FF_X74_Y160_N43 ; ; vx_fetch|VX_Warp_one|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1667: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.681 ; 84 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.201 ; 3.209 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.173 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.201 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1668: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.202 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.682 ; 84 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.202 ; 3.210 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.174 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1669: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.483 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1670: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.483 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1671: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.483 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1672: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.136 ; -; Data Required Time ; 5.483 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.138 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.136 ; 3.138 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; -; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1673: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.113 ; -; Data Required Time ; 5.460 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.115 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.113 ; 3.115 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; -; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1674: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.852 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.230 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.258 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; -; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1675: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.831 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.207 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; -; 6.235 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1676: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.727 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.154 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; -; 6.236 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1677: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.809 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.225 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.252 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1678: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.437 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.235 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; -; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1679: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.462 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.466 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.236 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; -; 6.264 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1680: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.730 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.166 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; -; 6.253 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1681: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.220 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; -; 6.247 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1682: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.787 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.443 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.472 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.477 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.224 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; -; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1683: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.380 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.407 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.412 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.160 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.252 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1684: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.409 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.436 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.442 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.221 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; -; 6.249 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1685: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.786 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.079 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.429 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.458 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.463 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.169 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.248 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1686: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_d_e_reg|b_reg_data[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.208 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.770 ; 86 ; 0.108 ; 0.905 ; -; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.206 ; 3.208 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.177 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; -; 6.206 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1687: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|PC_next_out[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.056 ; -; Data Required Time ; 5.403 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.073 ; ; ; ; ; ; -; Data Delay ; 3.064 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.567 ; 84 ; 0.115 ; 0.829 ; -; Cell ; ; 10 ; 0.372 ; 12 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.056 ; 3.064 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.056 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; -; 6.056 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; -; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1688: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.725 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.156 ; 0.716 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|datad ; -; 6.248 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1689: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.744 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.175 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~981|datad ; -; 6.255 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X102_Y147_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~981|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1690: Setup slack is -0.653 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|warp_num[1]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.653 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.208 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.644 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.206 ; 3.208 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.113 ; 0.698 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|datac ; -; 6.206 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|combout ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE|d ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N28 ; ; vx_d_e_reg|warp_num[1]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1691: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.704 ; 83 ; 0.125 ; 0.708 ; -; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.251 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; -; 3.762 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.767 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.892 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.918 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.923 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.279 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.369 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.374 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.057 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.148 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.154 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.862 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.890 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.896 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.176 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.251 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1692: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.199 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.207 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.679 ; 84 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.199 ; 3.207 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; -; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.171 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1693: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.241 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.630 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.490 ; 15 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.239 ; 3.241 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.445 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.471 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.165 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.239 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1694: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.640 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.883 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.913 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.919 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.179 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.254 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1695: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.547 ; 78 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.575 ; 18 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.239 ; 3.247 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.132 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.239 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1696: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.113 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.115 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; -; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.113 ; 3.115 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; -; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1697: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.729 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.158 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; -; 6.251 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1698: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.522 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.208 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; -; 6.235 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1699: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.737 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.502 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.166 ; 0.664 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; -; 6.252 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1700: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.201 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; -; 6.229 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1701: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.413 ; 74 ; 0.118 ; 0.683 ; -; Cell ; ; 14 ; 0.708 ; 22 ; 0.000 ; 0.134 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.239 ; 3.247 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.105 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.239 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1702: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.223 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; -; 6.251 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1703: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.230 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.257 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1704: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.233 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.233 ; 3.235 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.347 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.427 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.432 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.205 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.233 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1705: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[14] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.153 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.205 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.484 ; 78 ; 0.115 ; 0.747 ; -; Cell ; ; 16 ; 0.546 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.175 ; 5 ; 0.175 ; 0.175 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; -; 6.153 ; 3.205 ; ; ; ; ; ; data path ; -; 3.123 ; 0.175 ; FF ; uTco ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14]|q ; -; 3.191 ; 0.068 ; FF ; CELL ; 3 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]~la_lab/laboutt[12] ; -; 3.866 ; 0.675 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10|datad ; -; 3.939 ; 0.073 ; FF ; CELL ; 2 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10~la_lab/laboutt[5] ; -; 4.100 ; 0.156 ; FF ; IC ; 1 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16|datac ; -; 4.187 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16|combout ; -; 4.192 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16~la_mlab/laboutb[12] ; -; 4.393 ; 0.201 ; FF ; IC ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19|datab ; -; 4.514 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19|combout ; -; 4.520 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19~la_mlab/laboutb[5] ; -; 4.635 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datac ; -; 4.718 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.722 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.155 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.182 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.188 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.345 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.373 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.378 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.125 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.153 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1706: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.264 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.266 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.832 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.264 ; 3.266 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; -; 6.238 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; -; 6.264 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; -; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1707: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.425 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.425 ; 0.020 ; ; uTsu ; 1 ; FF_X80_Y155_N25 ; ; vx_d_e_reg|PC_next_out[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1708: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.214 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.685 ; 84 ; 0.128 ; 0.940 ; -; Cell ; ; 12 ; 0.404 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.206 ; 3.214 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.176 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.206 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1709: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.779 ; 86 ; 0.114 ; 1.228 ; -; Cell ; ; 12 ; 0.342 ; 11 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.124 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; -; 6.241 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1710: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.881 ; 89 ; 0.127 ; 1.317 ; -; Cell ; ; 12 ; 0.251 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.226 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; -; 6.252 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1711: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; -; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.256 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1712: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.868 ; 88 ; 0.106 ; 1.378 ; -; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.216 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.246 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1713: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.615 ; 80 ; 0.128 ; 0.769 ; -; Cell ; ; 14 ; 0.529 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.261 ; 3.269 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.022 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; -; 6.051 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; -; 6.057 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; -; 6.185 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; -; 6.261 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; -; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1714: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.727 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.160 ; 0.607 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|datad ; -; 6.247 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1715: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.732 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.215 ; 0.693 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~751|dataf ; -; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y164_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~751|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1716: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.267 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.028 ; ; ; ; ; ; -; Data Delay ; 3.269 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.267 ; 3.269 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.238 ; 0.670 ; RR ; IC ; 1 ; MLABCELL_X109_Y153_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1002|dataf ; -; 6.267 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X109_Y153_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1002|combout ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10]|d ; -; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; -; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.175 ; ; uTsu ; 1 ; FF_X109_Y153_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1717: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.796 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.229 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~676|dataf ; -; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~676|combout ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4]|d ; -; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1718: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|warp_num[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.206 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.208 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.644 ; 82 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.206 ; 3.208 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.113 ; 0.698 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|datac ; -; 6.206 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|combout ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1]|d ; -; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.166 ; ; uTsu ; 1 ; FF_X80_Y153_N29 ; ; vx_d_e_reg|warp_num[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1719: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.736 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.495 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[13] ; -; 6.219 ; 0.724 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~959|dataf ; -; 6.247 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~959|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y143_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1720: Setup slack is -0.652 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.652 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.232 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|dataf ; -; 6.260 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y146_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1721: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.199 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.201 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.619 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.199 ; 3.201 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.171 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1722: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.200 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.202 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.200 ; 3.202 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.172 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.200 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1723: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.655 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.479 ; 15 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.253 ; 3.261 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.942 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.063 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.169 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.175 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.290 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.316 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.321 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.084 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.162 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.168 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.882 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.912 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.178 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.253 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1724: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.547 ; 78 ; 0.116 ; 0.686 ; -; Cell ; ; 14 ; 0.574 ; 18 ; 0.000 ; 0.114 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.238 ; 3.246 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; -; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; -; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; -; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; -; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.132 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.238 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1725: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1726: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1727: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.847 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.227 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; -; 6.255 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1728: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.222 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.250 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1729: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.375 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.404 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.408 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.226 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.255 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1730: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.612 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.805 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.506 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; -; 6.237 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; -; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; -; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1731: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.233 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.233 ; 3.235 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.514 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.207 ; 0.693 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; -; 6.233 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1732: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.226 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.712 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.224 ; 3.226 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.397 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.473 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.197 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; -; 6.224 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1733: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.302 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; -; 5.331 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; -; 5.335 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; -; 6.228 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; -; 6.255 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1734: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.587 ; 80 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.534 ; 16 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.238 ; 3.246 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.131 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.238 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1735: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.269 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.269 ; 3.271 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.437 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.176 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; -; 6.269 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; -; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1736: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.804 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.466 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.240 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; -; 6.268 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1737: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.215 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.217 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.728 ; 85 ; 0.108 ; 0.861 ; -; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.215 ; 3.217 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.186 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; -; 6.215 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1738: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_d_e_reg|csr_mask[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.215 ; -; Data Required Time ; 5.564 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.066 ; ; ; ; ; ; -; Data Delay ; 3.217 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.729 ; 85 ; 0.108 ; 0.862 ; -; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.215 ; 3.217 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.187 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; -; 6.215 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; -; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; -; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1739: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.363 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.282 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.312 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.316 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.169 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.255 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1740: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.755 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.380 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.407 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.412 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.160 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; -; 6.252 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1741: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|csr_address[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.163 ; -; Data Required Time ; 5.512 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.121 ; ; ; ; ; ; -; Data Delay ; 3.165 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.670 ; 84 ; 0.119 ; 0.821 ; -; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.083 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.163 ; 3.165 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.307 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.090 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; -; 6.163 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; -; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; -; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; -; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1742: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N29 ; ; vx_d_e_reg|PC_next_out[31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1743: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N19 ; ; vx_d_e_reg|PC_next_out[28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1744: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[23] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N5 ; ; vx_d_e_reg|PC_next_out[23] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1745: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N7 ; ; vx_d_e_reg|PC_next_out[24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1746: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.426 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N1 ; ; vx_d_e_reg|PC_next_out[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1747: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_f_d_reg|curr_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.121 ; -; Data Required Time ; 5.470 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.123 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.742 ; 88 ; 0.119 ; 1.398 ; -; Cell ; ; 10 ; 0.261 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.121 ; 3.123 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.356 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.690 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.718 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.723 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.121 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; -; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1748: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.202 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.210 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.515 ; 78 ; 0.118 ; 0.935 ; -; Cell ; ; 12 ; 0.569 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.202 ; 3.210 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.174 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.202 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.202 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.202 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1749: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.880 ; 89 ; 0.127 ; 1.316 ; -; Cell ; ; 12 ; 0.251 ; 8 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.225 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; -; 6.251 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1750: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.813 ; 87 ; 0.114 ; 1.354 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.218 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.246 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1751: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.725 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.156 ; 0.716 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|datad ; -; 6.248 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1752: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.413 ; 0.485 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|datad ; -; 5.489 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|combout ; -; 5.494 ; 0.005 ; RR ; CELL ; 17 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17~la_lab/laboutb[3] ; -; 6.207 ; 0.713 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~559|dataf ; -; 6.235 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~559|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y164_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1753: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.223 ; 0.669 ; RR ; IC ; 1 ; LABCELL_X104_Y158_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~715|dataf ; -; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y158_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~715|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11]|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y158_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1754: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.584 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.208 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|dataf ; -; 6.235 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y157_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1755: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.743 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.431 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.174 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|datac ; -; 6.254 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|combout ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]|d ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y151_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1756: Setup slack is -0.651 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|rs1[0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.203 ; -; Data Required Time ; 5.552 ; -; Slack ; -0.651 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.205 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.657 ; 83 ; 0.108 ; 0.868 ; -; Cell ; ; 12 ; 0.427 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.203 ; 3.205 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.126 ; 0.711 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N3 ; High Speed ; vx_d_e_reg|i316~0|datac ; -; 6.203 ; 0.077 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N3 ; High Speed ; vx_d_e_reg|i316~0|combout ; -; 6.203 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0]|d ; -; 6.203 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.552 ; 0.165 ; ; uTsu ; 1 ; FF_X81_Y153_N4 ; ; vx_d_e_reg|rs1[0] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1757: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.197 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.199 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.617 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.197 ; 3.199 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.169 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.197 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1758: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.199 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.207 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.633 ; 82 ; 0.138 ; 0.657 ; -; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.199 ; 3.207 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; -; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.171 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1759: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.632 ; 82 ; 0.138 ; 0.657 ; -; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.198 ; 3.206 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; -; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.170 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.198 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1760: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1761: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.462 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1762: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.164 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; -; 6.250 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1763: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.241 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.239 ; 3.241 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.211 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; -; 6.239 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1764: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.775 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.204 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; -; 6.232 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1765: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.241 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; -; 6.268 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1766: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.515 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.216 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; -; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1767: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.252 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1768: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.205 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; -; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1769: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[5] ; -; To Node ; vx_e_m_reg|alu_result[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.153 ; -; Data Required Time ; 5.503 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.084 ; ; ; ; ; ; -; Data Delay ; 3.204 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.322 ; 79 ; 0.000 ; 2.322 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 4 ; 2.394 ; 75 ; 0.121 ; 1.030 ; -; Cell ; ; 12 ; 0.576 ; 18 ; 0.000 ; 0.131 ; -; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.949 ; 2.949 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.949 ; 2.322 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; -; 2.949 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; -; 6.153 ; 3.204 ; ; ; ; ; ; data path ; -; 3.183 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5]|q ; -; 3.247 ; 0.064 ; RR ; CELL ; 16 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]~la_lab/laboutb[10] ; -; 4.277 ; 1.030 ; RR ; IC ; 4 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|datad ; -; 4.408 ; 0.131 ; RF ; CELL ; 1 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|cout ; -; 4.408 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N18 ; High Speed ; vx_execute|[0].vx_alu|add_0~25|cin ; -; 4.522 ; 0.114 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29|sumout ; -; 4.527 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29~la_lab/laboutt[15] ; -; 4.954 ; 0.427 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|datac ; -; 5.041 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|combout ; -; 5.047 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51~la_mlab/laboutt[13] ; -; 5.168 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datac ; -; 5.258 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; -; 5.264 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; -; 6.080 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; -; 6.153 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; -; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; -; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1770: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+----------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.186 ; -; Data Required Time ; 5.536 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+-------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.082 ; ; ; ; ; ; -; Data Delay ; 3.188 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.633 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.433 ; 14 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.186 ; 3.188 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.104 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; -; 6.186 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; -; 6.186 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|d ; -; 6.186 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|clk ; -; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.536 ; 0.150 ; ; uTsu ; 1 ; FF_X79_Y151_N58 ; ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1771: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.227 ; 3.229 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.199 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; -; 6.227 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1772: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.587 ; 80 ; 0.117 ; 0.710 ; -; Cell ; ; 14 ; 0.533 ; 16 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.237 ; 3.245 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.131 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.237 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1773: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.051 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; -; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; -; 6.222 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; -; 6.248 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1774: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.730 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.190 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.217 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.222 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.164 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; -; 6.246 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1775: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.380 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.457 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.462 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.219 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1776: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|PC_next_out[25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.077 ; -; Data Required Time ; 5.427 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.063 ; ; ; ; ; ; -; Data Delay ; 3.079 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.077 ; 3.079 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|sclr ; -; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; -; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; -; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.427 ; 0.022 ; ; uTsu ; 1 ; FF_X80_Y155_N11 ; ; vx_d_e_reg|PC_next_out[25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1777: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.815 ; 87 ; 0.110 ; 1.366 ; -; Cell ; ; 12 ; 0.311 ; 10 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.217 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; -; 6.245 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1778: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.750 ; 84 ; 0.106 ; 1.220 ; -; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.148 ; 1.220 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|datab ; -; 6.268 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; -; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1779: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.727 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.160 ; 0.607 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|datad ; -; 6.247 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1780: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.263 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.265 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.745 ; 84 ; 0.106 ; 1.215 ; -; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.263 ; 3.265 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.143 ; 1.215 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~610|datab ; -; 6.263 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~610|combout ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2]|d ; -; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1781: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.725 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.252 ; 0.326 ; RR ; IC ; 1 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|datac ; -; 5.331 ; 0.079 ; RF ; CELL ; 2 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|combout ; -; 5.335 ; 0.004 ; FF ; CELL ; 23 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19~la_lab/laboutb[16] ; -; 6.226 ; 0.891 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~622|dataf ; -; 6.255 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X101_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~622|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1782: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.792 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; -; 6.226 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~607|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~607|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.166 ; ; uTsu ; 1 ; FF_X99_Y145_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1783: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.158 ; 0.559 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~517|datac ; -; 6.241 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~517|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y163_N14 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1784: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.585 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.208 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|dataf ; -; 6.235 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y157_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1785: Setup slack is -0.650 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.650 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.743 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.431 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.174 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|datac ; -; 6.254 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|combout ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE|d ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y151_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1786: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.196 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.204 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.630 ; 82 ; 0.138 ; 0.657 ; -; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.196 ; 3.204 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; -; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.168 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.196 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1787: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.844 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.223 ; 0.741 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; -; 6.249 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1788: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.241 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.239 ; 3.241 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.211 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; -; 6.239 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1789: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; -; 6.252 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1790: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.733 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.502 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; -; 6.162 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; -; 6.241 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1791: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.219 ; 0.890 ; RR ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; -; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1792: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.808 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.300 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; -; 5.329 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; -; 5.333 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; -; 6.226 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; -; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1793: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.222 ; -; Data Required Time ; 5.573 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.056 ; ; ; ; ; ; -; Data Delay ; 3.224 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.372 ; 12 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.222 ; 3.224 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.395 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.471 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.475 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.195 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; -; 6.222 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; -; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1794: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.726 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.456 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.487 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.491 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.163 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; -; 6.255 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1795: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_d_e_reg|csr_address[1] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.154 ; -; Data Required Time ; 5.505 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.125 ; ; ; ; ; ; -; Data Delay ; 3.156 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.675 ; 85 ; 0.119 ; 0.840 ; -; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.154 ; 3.156 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.081 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; -; 6.154 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; -; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; -; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; -; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1796: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.369 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.446 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.450 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.218 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; -; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1797: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.200 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.202 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.632 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.128 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.200 ; 3.202 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.072 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; -; 6.200 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; -; 6.200 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; -; 6.200 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1798: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 85 ; 0.096 ; 1.046 ; -; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.493 ; 0.096 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.569 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.574 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.620 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.646 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.650 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.775 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.799 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.805 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.388 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.417 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.422 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.164 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.244 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1799: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.813 ; 87 ; 0.114 ; 1.354 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.218 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.246 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1800: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.832 ; 87 ; 0.104 ; 1.354 ; -; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.216 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.244 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1801: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.868 ; 88 ; 0.106 ; 1.378 ; -; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.216 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.246 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1802: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[1] ; -; To Node ; vx_e_m_reg|alu_result[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.463 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.168 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.542 ; 80 ; 0.127 ; 0.625 ; -; Cell ; ; 16 ; 0.443 ; 14 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; -; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; -; 6.112 ; 3.168 ; ; ; ; ; ; data path ; -; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; -; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; -; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; -; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; -; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; -; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; -; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; -; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; -; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.440 ; 0.153 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29|dataf ; -; 5.468 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29|combout ; -; 5.472 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29~la_lab/laboutt[6] ; -; 6.087 ; 0.615 ; FF ; IC ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|dataf ; -; 6.112 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|combout ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|d ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.363 ; 2.863 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|clk ; -; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; -; 5.363 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.333 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.463 ; 0.130 ; ; uTsu ; 1 ; FF_X45_Y153_N22 ; ; vx_e_m_reg|alu_result[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1803: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.161 ; 0.608 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~666|datad ; -; 6.243 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X97_Y143_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~666|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1804: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.226 ; 0.872 ; FF ; IC ; 1 ; LABCELL_X108_Y150_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~281|dataf ; -; 6.254 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X108_Y150_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~281|combout ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25]|d ; -; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y150_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1805: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.232 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|dataf ; -; 6.260 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|combout ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE|d ; -; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.166 ; ; uTsu ; 1 ; FF_X103_Y146_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1806: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.110 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.112 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.652 ; 85 ; 0.119 ; 1.143 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.110 ; 3.112 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.110 ; 1.143 ; FF ; IC ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21]|ena ; -; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y156_N49 ; ; vx_f_d_reg|curr_PC[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1807: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.110 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.112 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.652 ; 85 ; 0.119 ; 1.143 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.110 ; 3.112 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.110 ; 1.143 ; FF ; IC ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3]|ena ; -; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y156_N40 ; ; vx_f_d_reg|curr_PC[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1808: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.262 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.264 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.737 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.262 ; 3.264 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.169 ; 0.626 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1014|datac ; -; 6.262 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1014|combout ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22]|d ; -; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.177 ; ; uTsu ; 1 ; FF_X98_Y142_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1809: Setup slack is -0.649 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.649 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.229 ; 0.737 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|dataf ; -; 6.255 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1810: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.197 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.205 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.696 ; 84 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.197 ; 3.205 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; -; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.169 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.197 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1811: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.196 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.204 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.695 ; 84 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.196 ; 3.204 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; -; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.168 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.196 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1812: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.578 ; 80 ; 0.127 ; 0.712 ; -; Cell ; ; 14 ; 0.536 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; -; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.428 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.454 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.460 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.172 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.234 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1813: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[24] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.060 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.628 ; 81 ; 0.192 ; 0.712 ; -; Cell ; ; 14 ; 0.506 ; 16 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; -; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; -; 6.234 ; 3.257 ; ; ; ; ; ; data path ; -; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; -; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; -; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; -; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.428 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.454 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.460 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.172 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.234 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1814: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1815: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1816: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.112 ; -; Data Required Time ; 5.464 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.021 ; ; ; ; ; ; -; Data Delay ; 3.114 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.112 ; 3.114 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; -; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; -; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; -; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1817: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.166 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; -; 6.252 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; -; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1818: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.785 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.167 ; 0.258 ; FF ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; -; 5.194 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; -; 5.200 ; 0.006 ; RR ; CELL ; 29 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[1] ; -; 6.163 ; 0.963 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|datac ; -; 6.241 ; 0.078 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.162 ; ; uTsu ; 1 ; FF_X102_Y162_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1819: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.270 ; -; Data Required Time ; 5.622 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.272 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.813 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.270 ; 3.272 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.493 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.524 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.528 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.243 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; -; 6.270 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; -; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1820: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.367 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.396 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.400 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.218 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.247 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1821: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.764 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.483 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.202 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; -; 6.229 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; -; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; -; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1822: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.207 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.235 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1823: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.042 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.207 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; -; 6.235 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; -; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1824: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.238 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.240 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.771 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.238 ; 3.240 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.272 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.299 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.305 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.210 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; -; 6.238 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; -; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1825: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.844 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.223 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.251 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1826: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.254 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.846 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.254 ; 3.256 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.227 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.254 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1827: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.802 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.165 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; -; 6.248 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; -; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1828: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.810 ; 87 ; 0.114 ; 1.351 ; -; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.215 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; -; 6.243 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1829: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.246 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1830: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.175 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 1.871 ; 86 ; 0.742 ; 1.129 ; -; Cell ; ; 6 ; 0.171 ; 8 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; -; 6.248 ; 2.175 ; ; ; ; ; ; data path ; -; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N44 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|q ; -; 4.250 ; 0.044 ; FF ; CELL ; 2 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[9] ; -; 4.992 ; 0.742 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datad ; -; 5.084 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.090 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.219 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; -; 6.248 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1831: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.170 ; 0.730 ; RR ; IC ; 1 ; MLABCELL_X101_Y146_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~693|datad ; -; 6.256 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y146_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~693|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y146_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1832: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.215 ; -; Data Required Time ; 5.567 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.061 ; ; ; ; ; ; -; Data Delay ; 3.217 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.701 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.162 ; 79 ; 0.000 ; 2.162 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.215 ; 3.217 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.363 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; -; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; -; 5.396 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; -; 6.133 ; 0.737 ; RR ; IC ; 1 ; LABCELL_X87_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~397|datad ; -; 6.215 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X87_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~397|combout ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13]|d ; -; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.437 ; 2.937 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.227 ; 2.162 ; RR ; IC ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13]|clk ; -; 5.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; -; 5.437 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.407 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.567 ; 0.160 ; ; uTsu ; 1 ; FF_X87_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1833: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.203 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.605 ; 81 ; 0.192 ; 0.884 ; -; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.201 ; 3.203 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; -; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.173 ; 0.884 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.201 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1834: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[19] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.117 ; -; Data Required Time ; 5.469 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.119 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.117 ; 3.119 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19]|ena ; -; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N5 ; ; vx_f_d_reg|curr_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1835: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[12] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.117 ; -; Data Required Time ; 5.469 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.119 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.117 ; 3.119 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12]|ena ; -; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N49 ; ; vx_f_d_reg|curr_PC[12] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1836: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.117 ; -; Data Required Time ; 5.469 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.119 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; -; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.117 ; 3.119 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; -; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2]|ena ; -; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N13 ; ; vx_f_d_reg|curr_PC[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1837: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.170 ; 0.629 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|datac ; -; 6.250 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1838: Setup slack is -0.648 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.609 ; -; Slack ; -0.648 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.023 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.681 ; 82 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.495 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[13] ; -; 6.164 ; 0.669 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~946|datac ; -; 6.257 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y146_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~946|combout ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18]|d ; -; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18]|clk ; -; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; -; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.609 ; 0.164 ; ; uTsu ; 1 ; FF_X103_Y146_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1839: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[18] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.194 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.202 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.693 ; 84 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; -; 6.194 ; 3.202 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; -; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; -; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.166 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.194 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1840: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.608 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.686 ; 82 ; 0.107 ; 0.854 ; -; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.038 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; -; 6.066 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; -; 6.072 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; -; 6.179 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; -; 6.255 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; -; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1841: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; -; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.078 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.011 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; -; 6.041 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; -; 6.047 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; -; 6.177 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; -; 6.253 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; -; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1842: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.252 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.254 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.252 ; 3.254 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; -; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; -; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; -; 6.225 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; -; 6.252 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; -; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1843: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.795 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.173 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|datad ; -; 6.253 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1844: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.838 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.217 ; 0.735 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|dataf ; -; 6.243 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1845: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.221 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1846: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.385 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.358 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; -; 5.436 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; -; 5.441 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; -; 6.209 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; -; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1847: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.210 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|dataf ; -; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|combout ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|d ; -; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y161_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1848: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_d_e_reg|b_reg_data[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.653 ; 83 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.425 ; 13 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.198 ; 3.200 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.124 ; 0.770 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|datae ; -; 6.198 ; 0.074 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|combout ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|d ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1849: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.220 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; -; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1850: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.782 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.221 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1851: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.074 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.413 ; 74 ; 0.118 ; 0.683 ; -; Cell ; ; 14 ; 0.704 ; 22 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.235 ; 3.243 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.105 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.235 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1852: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.668 ; 82 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.414 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.418 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.154 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.236 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1853: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.740 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.175 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; -; 6.261 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1854: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.733 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.219 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; -; 6.245 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1855: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.037 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.725 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.190 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; -; 5.217 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; -; 5.222 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; -; 6.159 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; -; 6.241 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1856: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.228 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.230 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.753 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.228 ; 3.230 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.342 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.427 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.200 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; -; 6.228 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; -; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; -; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1857: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.551 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.680 ; 84 ; 0.128 ; 0.935 ; -; Cell ; ; 12 ; 0.401 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.198 ; 3.206 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.170 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.198 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1858: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.721 ; 84 ; 0.104 ; 1.228 ; -; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.116 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; -; 6.236 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1859: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.832 ; 87 ; 0.104 ; 1.354 ; -; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.216 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; -; 6.244 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1860: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.150 ; -; Data Required Time ; 5.503 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.202 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.548 ; 80 ; 0.096 ; 0.816 ; -; Cell ; ; 14 ; 0.531 ; 17 ; 0.000 ; 0.122 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; 6.150 ; 3.202 ; ; ; ; ; ; data path ; -; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; -; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; -; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; -; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; -; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; -; 4.457 ; 0.493 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31|datae ; -; 4.531 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31|combout ; -; 4.535 ; 0.004 ; RR ; CELL ; 7 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31~la_lab/laboutb[12] ; -; 4.669 ; 0.134 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9|datac ; -; 4.755 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9|combout ; -; 4.761 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9~la_mlab/laboutb[17] ; -; 4.857 ; 0.096 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|datab ; -; 4.979 ; 0.122 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; -; 4.985 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; -; 5.210 ; 0.225 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; -; 5.288 ; 0.078 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; -; 5.294 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; -; 6.078 ; 0.784 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; -; 6.150 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; -; 6.150 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; -; 6.150 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1861: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.849 ; 88 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.272 ; 8 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.211 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.241 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1862: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.265 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.267 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.750 ; 84 ; 0.106 ; 1.220 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.265 ; 3.267 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.148 ; 1.220 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~738|datab ; -; 6.265 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~738|combout ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2]|d ; -; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1863: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.272 ; -; Data Required Time ; 5.625 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.274 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.272 ; 3.274 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.244 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X103_Y148_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~914|dataf ; -; 6.272 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X103_Y148_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~914|combout ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18]|d ; -; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.625 ; 0.182 ; ; uTsu ; 1 ; FF_X103_Y148_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1864: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_d_e_reg|csr_mask[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.594 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.036 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.665 ; 82 ; 0.119 ; 0.840 ; -; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.154 ; 0.418 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N30 ; High Speed ; vx_d_e_reg|i531~22|datac ; -; 6.241 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X76_Y150_N30 ; High Speed ; vx_d_e_reg|i531~22|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22]|clk ; -; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22] ; -; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.594 ; 0.162 ; ; uTsu ; 1 ; FF_X76_Y150_N32 ; ; vx_d_e_reg|csr_mask[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1865: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.200 ; -; Data Required Time ; 5.553 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.208 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.620 ; 82 ; 0.192 ; 0.884 ; -; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.200 ; 3.208 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.172 ; 0.884 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.200 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1866: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.170 ; 0.629 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|datac ; -; 6.250 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y160_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1867: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.282 ; -; Data Required Time ; 5.635 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.091 ; ; ; ; ; ; -; Data Delay ; 2.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 3 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 3 ; 1.903 ; 85 ; 0.392 ; 0.786 ; -; Cell ; ; 8 ; 0.191 ; 9 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|clk ; -; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; -; 6.282 ; 2.227 ; ; ; ; ; ; data path ; -; 4.188 ; 0.133 ; FF ; uTco ; 1 ; FF_X92_Y148_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|q ; -; 4.231 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[9] ; -; 4.956 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|dataf ; -; 4.982 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; -; 4.987 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; -; 5.773 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; -; 5.799 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; -; 5.804 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; -; 6.196 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; -; 6.282 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; -; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; -; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; -; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1868: Setup slack is -0.647 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.647 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.262 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.745 ; 84 ; 0.106 ; 1.215 ; -; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.260 ; 3.262 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.143 ; 1.215 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~994|datab ; -; 6.260 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~994|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1869: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[7] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.694 ; 83 ; 0.116 ; 1.036 ; -; Cell ; ; 14 ; 0.435 ; 13 ; 0.000 ; 0.095 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; -; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; -; 6.245 ; 3.252 ; ; ; ; ; ; data path ; -; 3.116 ; 0.123 ; FF ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; -; 3.191 ; 0.075 ; FF ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; -; 4.227 ; 1.036 ; FF ; IC ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179|datae ; -; 4.322 ; 0.095 ; FR ; CELL ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179|combout ; -; 4.328 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179~la_mlab/laboutt[19] ; -; 4.444 ; 0.116 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datad ; -; 4.524 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; -; 4.529 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; -; 5.045 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; -; 5.071 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; -; 5.075 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; -; 5.202 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; -; 5.285 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.289 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.066 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.092 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.097 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.219 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.245 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; -; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1870: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|wb[0] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.195 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.598 ; 81 ; 0.123 ; 0.657 ; -; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; -; 6.195 ; 3.197 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; -; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; -; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; -; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; -; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; -; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.167 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.195 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1871: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|wb[0] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.194 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.196 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.597 ; 81 ; 0.123 ; 0.657 ; -; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; -; 6.194 ; 3.196 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; -; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; -; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; -; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; -; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; -; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.166 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.194 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1872: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.251 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.253 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.729 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.251 ; 3.253 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.158 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; -; 6.251 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|d ; -; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X103_Y161_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1873: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.221 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X99_Y145_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1874: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; -; 6.221 ; 0.685 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|dataf ; -; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1875: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.200 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.076 ; ; ; ; ; ; -; Data Delay ; 3.202 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.743 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.200 ; 3.202 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.337 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.367 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.371 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.173 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; -; 6.200 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; -; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; -; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1876: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.206 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; -; 6.234 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1877: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.783 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.227 ; 3.229 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.481 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; -; 6.200 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; -; 6.227 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; -; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1878: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.747 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.086 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.164 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; -; 6.250 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1879: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.668 ; 82 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.414 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.418 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.154 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; -; 6.236 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; -; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1880: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.781 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.432 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.464 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.468 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.219 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; -; 6.245 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1881: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.583 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.766 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.202 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; -; 6.229 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1882: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.590 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.270 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.297 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.303 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; -; 6.208 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; -; 6.236 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1883: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_d_e_reg|b_reg_data[17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.552 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.078 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.632 ; 82 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.446 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.198 ; 3.200 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.072 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; -; 6.198 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; -; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; -; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1884: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.196 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.204 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.510 ; 78 ; 0.118 ; 0.930 ; -; Cell ; ; 12 ; 0.568 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.196 ; 3.204 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.169 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.196 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.196 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.196 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1885: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.829 ; 87 ; 0.104 ; 1.351 ; -; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.213 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; -; 6.241 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1886: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[22] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.682 ; 84 ; 0.115 ; 0.944 ; -; Cell ; ; 12 ; 0.402 ; 13 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.201 ; 3.209 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.172 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; -; 6.201 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; -; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; -; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1887: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.681 ; 84 ; 0.115 ; 0.943 ; -; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.201 ; 3.209 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.171 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; -; 6.201 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; -; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; -; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1888: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; -; Launch Clock ; clk (INVERTED) ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 1.500 ; ; ; ; ; ; -; Clock Skew ; -0.107 ; ; ; ; ; ; -; Data Delay ; 2.174 ; ; ; ; ; ; -; Number of Logic Levels ; ; 2 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; -; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 2 ; 1.870 ; 86 ; 0.742 ; 1.128 ; -; Cell ; ; 6 ; 0.171 ; 8 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ -; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; -; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; -; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|clk ; -; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; -; 6.247 ; 2.174 ; ; ; ; ; ; data path ; -; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N44 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|q ; -; 4.250 ; 0.044 ; FF ; CELL ; 2 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[9] ; -; 4.992 ; 0.742 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datad ; -; 5.084 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; -; 5.090 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; -; 6.218 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; -; 6.247 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; -; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1889: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.201 ; -; Data Required Time ; 5.555 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.076 ; ; ; ; ; ; -; Data Delay ; 3.203 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.741 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.201 ; 3.203 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.336 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; -; 5.363 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; -; 5.369 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[19] ; -; 6.173 ; 0.804 ; RR ; IC ; 1 ; LABCELL_X83_Y160_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~273|dataf ; -; 6.201 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X83_Y160_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~273|combout ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17]|d ; -; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17]|clk ; -; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; -; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.555 ; 0.163 ; ; uTsu ; 1 ; FF_X83_Y160_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1890: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.043 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.723 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.154 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~968|datac ; -; 6.237 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~968|combout ; -; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8]|d ; -; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8]|clk ; -; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; -; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y163_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1891: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.268 ; -; Data Required Time ; 5.622 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.011 ; ; ; ; ; ; -; Data Delay ; 3.270 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.268 ; 3.270 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.241 ; 0.718 ; FF ; IC ; 1 ; LABCELL_X108_Y155_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~743|dataf ; -; 6.268 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X108_Y155_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~743|combout ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7]|d ; -; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.487 ; 2.987 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; -; 5.487 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; -; 5.457 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.622 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y155_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1892: Setup slack is -0.646 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.257 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.646 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.259 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.257 ; 3.259 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; -; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; -; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; -; 6.231 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X98_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~869|dataf ; -; 6.257 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~869|combout ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5]|d ; -; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1893: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.240 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.620 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.494 ; 15 ; 0.000 ; 0.113 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.232 ; 3.240 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.438 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.464 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.470 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.158 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.232 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1894: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+----------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------+ -; Property ; Value ; -+--------------------+-------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+-------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.633 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.480 ; 15 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.438 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.464 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.470 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.158 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.232 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1895: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|rd[4] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.643 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; -; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; -; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; -; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; -; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.876 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.906 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.912 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.172 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.247 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1896: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.602 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.630 ; 81 ; 0.115 ; 0.763 ; -; Cell ; ; 14 ; 0.499 ; 15 ; 0.000 ; 0.113 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.247 ; 3.255 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.876 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; -; 5.906 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; -; 5.912 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; -; 6.172 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; -; 6.247 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1897: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-----------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------+ -; Property ; Value ; -+--------------------+--------------------------+ -; From Node ; vx_d_e_reg|a_reg_data[3] ; -; To Node ; vx_e_m_reg|alu_result[2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.146 ; -; Data Required Time ; 5.501 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+--------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.072 ; ; ; ; ; ; -; Data Delay ; 3.209 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.310 ; 79 ; 0.000 ; 2.310 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.590 ; 81 ; 0.109 ; 0.927 ; -; Cell ; ; 14 ; 0.436 ; 14 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.937 ; 2.937 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.937 ; 2.310 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; -; 2.937 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; -; 6.146 ; 3.209 ; ; ; ; ; ; data path ; -; 3.120 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3]|q ; -; 3.167 ; 0.047 ; FF ; CELL ; 16 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]~la_lab/laboutb[1] ; -; 4.094 ; 0.927 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|datad ; -; 4.174 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|combout ; -; 4.179 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27~la_lab/laboutt[5] ; -; 4.288 ; 0.109 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataa ; -; 4.415 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; -; 4.419 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; -; 4.636 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; -; 4.711 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; -; 4.715 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; -; 5.148 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; -; 5.175 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; -; 5.181 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; -; 5.338 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; -; 5.366 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; -; 5.371 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; -; 6.118 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; -; 6.146 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; -; 6.146 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; -; 6.146 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1898: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|wb[0] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.194 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.595 ; 81 ; 0.123 ; 0.657 ; -; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; -; 6.192 ; 3.194 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; -; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; -; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; -; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; -; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; -; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.164 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1899: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.222 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.053 ; ; ; ; ; ; -; Data Delay ; 3.224 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.222 ; 3.224 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.405 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.485 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.490 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; -; 6.195 ; 0.705 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|dataf ; -; 6.222 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|combout ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|d ; -; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|clk ; -; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y162_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1900: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.169 ; 0.604 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|datad ; -; 6.249 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y147_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1901: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.776 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.094 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.487 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.516 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.521 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.156 ; 0.635 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|datac ; -; 6.250 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|combout ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|d ; -; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1902: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.250 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.252 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.250 ; 3.252 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; -; 6.222 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; -; 6.250 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; -; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1903: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.227 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.229 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.773 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.227 ; 3.229 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.199 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; -; 6.227 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; -; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1904: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.769 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.479 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.208 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; -; 6.236 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1905: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.209 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; -; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1906: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.245 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.247 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.799 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.245 ; 3.247 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.218 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; -; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; -; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1907: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.034 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; -; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; -; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; -; 6.219 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; -; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; -; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1908: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.767 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.445 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.477 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.205 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; -; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1909: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.258 ; -; Data Required Time ; 5.613 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.260 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.728 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.258 ; 3.260 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.432 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; -; 5.464 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; -; 5.468 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; -; 6.166 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; -; 6.258 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; -; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1910: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.752 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.372 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.217 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; -; 6.243 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1911: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.039 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.770 ; 85 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.351 ; 11 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.375 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.452 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.457 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.214 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; -; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; -; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1912: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.756 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.374 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.276 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; -; 5.306 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; -; 5.310 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; -; 6.163 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; -; 6.249 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; -; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1913: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.731 ; 84 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; -; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; -; 5.521 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[4] ; -; 6.213 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~764|dataf ; -; 6.241 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~764|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y144_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1914: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.225 ; -; Data Required Time ; 5.580 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.227 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.763 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.225 ; 3.227 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; -; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; -; 5.569 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[7] ; -; 6.197 ; 0.628 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1001|dataf ; -; 6.225 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1001|combout ; -; 6.225 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9]|d ; -; 6.225 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.580 ; 0.164 ; ; uTsu ; 1 ; FF_X89_Y159_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1915: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.610 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.720 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.416 ; 13 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.522 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[6] ; -; 6.169 ; 0.647 ; FF ; IC ; 1 ; MLABCELL_X96_Y161_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~742|datac ; -; 6.255 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X96_Y161_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~742|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.610 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y161_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1916: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.114 ; -; Data Required Time ; 5.469 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.116 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.657 ; 85 ; 0.119 ; 1.148 ; -; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.114 ; 3.116 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; -; 6.114 ; 1.148 ; FF ; IC ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9]|ena ; -; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X69_Y159_N46 ; ; vx_f_d_reg|curr_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1917: Setup slack is -0.645 (VIOLATED) -=============================================================================== -+---------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------+ -; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; To Node ; vx_e_m_reg|alu_result[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.147 ; -; Data Required Time ; 5.502 ; -; Slack ; -0.645 (VIOLATED) ; -+--------------------+------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.083 ; ; ; ; ; ; -; Data Delay ; 3.199 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.582 ; 81 ; 0.129 ; 0.816 ; -; Cell ; ; 14 ; 0.494 ; 15 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; -; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; -; 6.147 ; 3.199 ; ; ; ; ; ; data path ; -; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; -; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; -; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; -; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; -; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; -; 4.515 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11|datad ; -; 4.607 ; 0.092 ; FR ; CELL ; 1 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11|combout ; -; 4.613 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11~la_mlab/laboutb[5] ; -; 4.814 ; 0.201 ; RR ; IC ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38|datae ; -; 4.887 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38|combout ; -; 4.893 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38~la_mlab/laboutt[12] ; -; 5.022 ; 0.129 ; RR ; IC ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39|datad ; -; 5.094 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39|combout ; -; 5.098 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39~la_lab/laboutb[4] ; -; 5.392 ; 0.294 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40|datac ; -; 5.478 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40|combout ; -; 5.483 ; 0.005 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40~la_mlab/laboutb[8] ; -; 6.074 ; 0.591 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datad ; -; 6.147 ; 0.073 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; -; 6.147 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; -; 6.147 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; -; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; -; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.502 ; 0.167 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1918: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.612 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.192 ; 3.200 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.164 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1919: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.193 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.201 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.613 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.193 ; 3.201 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.165 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.193 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1920: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.625 ; 82 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.192 ; 3.200 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; -; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.164 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1921: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.193 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.201 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.626 ; 82 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.193 ; 3.201 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; -; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.165 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.193 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1922: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.105 ; -; Data Required Time ; 5.461 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.024 ; ; ; ; ; ; -; Data Delay ; 3.107 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.601 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.105 ; 3.107 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.105 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|sload ; -; 6.105 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|clk ; -; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; -; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.461 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1923: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.099 ; -; Data Required Time ; 5.455 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.101 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.099 ; 3.101 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|sload ; -; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1924: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.099 ; -; Data Required Time ; 5.455 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.101 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.099 ; 3.101 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|sload ; -; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N26 ; ; vx_fetch|VX_Warp_zero|real_PC[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1925: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.671 ; 82 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; -; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; -; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; -; 6.150 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; -; 6.243 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1926: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.194 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.196 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.622 ; 82 ; 0.192 ; 0.922 ; -; Cell ; ; 12 ; 0.452 ; 14 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.194 ; 3.196 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; -; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; -; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; -; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.245 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.167 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.194 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1927: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.232 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.234 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.765 ; 85 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.232 ; 3.234 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.205 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; -; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; -; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1928: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.255 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.257 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.689 ; 83 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.446 ; 14 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.255 ; 3.257 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.175 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; -; 6.255 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; -; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1929: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.778 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.445 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.477 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.216 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; -; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; -; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1930: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.221 ; -; Data Required Time ; 5.577 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.058 ; ; ; ; ; ; -; Data Delay ; 3.223 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.760 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.221 ; 3.223 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.318 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; -; 5.347 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; -; 5.351 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; -; 6.195 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; -; 6.221 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; -; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; -; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; -; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1931: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.718 ; 84 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.407 ; 13 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.155 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; -; 5.184 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; -; 5.188 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; -; 6.153 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; -; 6.244 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1932: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.223 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.225 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.758 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.223 ; 3.225 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.442 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.471 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; -; 6.196 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; -; 6.223 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; -; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; -; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1933: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|b_reg_data[30] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.509 ; 78 ; 0.118 ; 0.929 ; -; Cell ; ; 12 ; 0.571 ; 18 ; 0.000 ; 0.130 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.198 ; 3.206 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.169 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; -; 6.198 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1934: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.823 ; 87 ; 0.104 ; 1.317 ; -; Cell ; ; 12 ; 0.301 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.218 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; -; 6.244 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; -; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1935: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.233 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.047 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.721 ; 84 ; 0.104 ; 1.228 ; -; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.233 ; 3.235 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.116 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; -; 6.233 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; -; 6.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; -; 6.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; -; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1936: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.790 ; 86 ; 0.106 ; 1.300 ; -; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.138 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.259 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1937: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.117 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; -; 6.243 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1938: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.259 ; -; Data Required Time ; 5.615 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.261 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.790 ; 86 ; 0.106 ; 1.300 ; -; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.259 ; 3.261 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.138 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; -; 6.259 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; -; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1939: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.596 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.862 ; 88 ; 0.106 ; 1.372 ; -; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.210 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; -; 6.240 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1940: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.597 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.849 ; 88 ; 0.104 ; 1.378 ; -; Cell ; ; 12 ; 0.272 ; 8 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 6.211 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; -; 6.241 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1941: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|b_reg_data[21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.198 ; -; Data Required Time ; 5.554 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.069 ; ; ; ; ; ; -; Data Delay ; 3.206 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.678 ; 84 ; 0.115 ; 0.940 ; -; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.090 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.198 ; 3.206 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; -; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 6.168 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; -; 6.198 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; -; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; -; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; -; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1942: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.236 ; -; Data Required Time ; 5.592 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.238 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.759 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.236 ; 3.238 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.209 ; 0.811 ; FF ; IC ; 1 ; MLABCELL_X98_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~646|dataf ; -; 6.236 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X98_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~646|combout ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6]|d ; -; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.592 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1943: Setup slack is -0.644 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.239 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.644 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.038 ; ; ; ; ; ; -; Data Delay ; 3.241 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.761 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.239 ; 3.241 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.211 ; 0.717 ; FF ; IC ; 1 ; MLABCELL_X107_Y154_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~900|dataf ; -; 6.239 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X107_Y154_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~900|combout ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4]|d ; -; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4]|clk ; -; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; -; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y154_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1944: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.190 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.198 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.610 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.190 ; 3.198 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; -; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; -; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; -; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.162 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.190 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1945: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.640 ; 83 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.192 ; 3.200 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; -; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.164 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1946: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.191 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.199 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.639 ; 82 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.191 ; 3.199 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; -; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.163 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.191 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1947: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.190 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.198 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.623 ; 82 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.190 ; 3.198 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; -; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.162 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.190 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1948: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[1] ; -; To Node ; vx_d_e_reg|upper_immed[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.191 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.193 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.534 ; 79 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; -; 6.191 ; 3.193 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; -; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; -; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.163 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; -; 6.191 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; -; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1949: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[1] ; -; To Node ; vx_d_e_reg|upper_immed[5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.549 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.194 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.535 ; 79 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; -; 6.192 ; 3.194 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; -; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; -; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.164 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; -; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; -; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1950: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|csr_mask[10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.670 ; 83 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.441 ; 14 ; 0.000 ; 0.107 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.230 ; 3.232 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.123 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; -; 6.230 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1951: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.099 ; -; Data Required Time ; 5.456 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.101 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.099 ; 3.101 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|sload ; -; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.456 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y160_N8 ; ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1952: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.745 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.244 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; -; 5.323 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; -; 5.327 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; -; 6.174 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; -; 6.261 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1953: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.033 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.213 ; 0.704 ; RR ; IC ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|dataf ; -; 6.242 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|combout ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|d ; -; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|clk ; -; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.164 ; ; uTsu ; 1 ; FF_X105_Y157_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1954: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.261 ; -; Data Required Time ; 5.618 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.026 ; ; ; ; ; ; -; Data Delay ; 3.263 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.745 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.261 ; 3.263 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.244 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; -; 5.323 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; -; 5.327 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; -; 6.174 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; -; 6.261 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|d ; -; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|clk ; -; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1955: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.219 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; -; 6.247 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1956: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.367 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; -; 5.396 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; -; 5.400 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; -; 6.218 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; -; 6.247 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; -; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1957: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.788 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.477 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; -; 6.206 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; -; 6.234 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1958: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.234 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.791 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.234 ; 3.236 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.207 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; -; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; -; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1959: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.786 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.230 ; 3.232 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.443 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.470 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.475 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.203 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; -; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1960: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.244 ; -; Data Required Time ; 5.601 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.246 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.076 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.244 ; 3.246 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.371 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.447 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.451 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.217 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; -; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; -; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1961: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.603 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.048 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.825 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; -; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; -; 6.218 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; -; 6.246 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; -; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; -; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1962: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.249 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.251 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.827 ; 87 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.249 ; 3.251 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; -; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; -; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; -; 6.222 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; -; 6.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; -; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1963: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.581 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.050 ; ; ; ; ; ; -; Data Delay ; 3.226 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.816 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.224 ; 3.226 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.197 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; -; 6.224 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; -; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1964: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_d_e_reg|csr_address[7] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.193 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.119 ; ; ; ; ; ; -; Data Delay ; 3.195 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.713 ; 85 ; 0.119 ; 0.922 ; -; Cell ; ; 12 ; 0.360 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.193 ; 3.195 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.244 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.166 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; -; 6.193 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; -; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1965: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.243 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.245 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.822 ; 87 ; 0.104 ; 1.316 ; -; Cell ; ; 12 ; 0.301 ; 9 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.243 ; 3.245 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.217 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; -; 6.243 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; -; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1966: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[13] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.759 ; 85 ; 0.104 ; 1.275 ; -; Cell ; ; 12 ; 0.362 ; 11 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; -; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; -; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; -; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.121 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.241 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1967: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------+ -; From Node ; vx_csr_handler|decode_csr_address[2] ; -; To Node ; vx_e_m_reg|csr_result[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.260 ; -; Data Required Time ; 5.617 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+--------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.009 ; ; ; ; ; ; -; Data Delay ; 3.271 ; ; ; ; ; ; -; Number of Logic Levels ; ; 7 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 7 ; 2.837 ; 87 ; 0.116 ; 0.924 ; -; Cell ; ; 16 ; 0.314 ; 10 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; -; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; -; 6.260 ; 3.271 ; ; ; ; ; ; data path ; -; 3.109 ; 0.120 ; FF ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; -; 3.156 ; 0.047 ; FF ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; -; 4.080 ; 0.924 ; FF ; IC ; 1 ; LABCELL_X25_Y153_N24 ; Mixed ; vx_csr_handler|Mux_3~315|dataf ; -; 4.110 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X25_Y153_N24 ; Low Power ; vx_csr_handler|Mux_3~315|combout ; -; 4.114 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X25_Y153_N24 ; Low Power ; vx_csr_handler|Mux_3~315~la_lab/laboutt[16] ; -; 4.454 ; 0.340 ; RR ; IC ; 1 ; LABCELL_X30_Y153_N48 ; Mixed ; vx_csr_handler|Mux_3~316|datad ; -; 4.534 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X30_Y153_N48 ; High Speed ; vx_csr_handler|Mux_3~316|combout ; -; 4.538 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X30_Y153_N48 ; High Speed ; vx_csr_handler|Mux_3~316~la_lab/laboutb[12] ; -; 4.671 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317|dataf ; -; 4.697 ; 0.026 ; RR ; CELL ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317|combout ; -; 4.703 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317~la_mlab/laboutt[12] ; -; 5.128 ; 0.425 ; RR ; IC ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339|dataf ; -; 5.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339|combout ; -; 5.158 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339~la_lab/laboutb[10] ; -; 5.274 ; 0.116 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|dataf ; -; 5.300 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; -; 5.304 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; -; 6.081 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; -; 6.107 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; -; 6.112 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; -; 6.234 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; -; 6.260 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; -; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; -; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; -; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; -; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.617 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1968: Setup slack is -0.643 (VIOLATED) -=============================================================================== -+----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+-------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+-------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.643 (VIOLATED) ; -+--------------------+-------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.250 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.768 ; 85 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.248 ; 3.250 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.276 ; 0.350 ; RR ; IC ; 1 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9|dataf ; -; 5.304 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9|combout ; -; 5.310 ; 0.006 ; FF ; CELL ; 17 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9~la_mlab/laboutt[4] ; -; 6.220 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X108_Y150_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~313|dataf ; -; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X108_Y150_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~313|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y150_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; -+---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1969: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.189 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.637 ; 82 ; 0.135 ; 0.657 ; -; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.189 ; 3.197 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; -; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.161 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.189 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1970: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_d_e_reg|rd[1] ; -; To Node ; vx_d_e_reg|upper_immed[4] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.189 ; -; Data Required Time ; 5.547 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.081 ; ; ; ; ; ; -; Data Delay ; 3.191 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.532 ; 79 ; 0.127 ; 0.657 ; -; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; -; 6.189 ; 3.191 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; -; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; -; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; -; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; -; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; -; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.161 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; -; 6.189 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1971: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.628 ; 81 ; 0.118 ; 0.708 ; -; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.241 ; 3.249 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 4.098 ; 0.331 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; -; 4.125 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.130 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.248 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.359 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.364 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.047 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.138 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.144 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.852 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.880 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.886 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.166 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.241 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1972: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|csr_mask[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.228 ; -; Data Required Time ; 5.586 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.236 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.628 ; 81 ; 0.138 ; 0.712 ; -; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.096 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.228 ; 3.236 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; -; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; -; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; -; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; -; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; -; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; -; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.422 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.448 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.454 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.166 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; -; 6.228 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; -; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; -; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1973: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_d_e_reg|csr_mask[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.229 ; -; Data Required Time ; 5.587 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.080 ; ; ; ; ; ; -; Data Delay ; 3.231 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.670 ; 83 ; 0.116 ; 0.788 ; -; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.106 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.229 ; 3.231 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; -; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; -; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; -; 6.123 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; -; 6.229 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; -; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; -; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; -; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1974: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_fetch|VX_Warp_zero|real_PC[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.099 ; -; Data Required Time ; 5.457 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.029 ; ; ; ; ; ; -; Data Delay ; 3.101 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; -; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.099 ; 3.101 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; -; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; -; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; -; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; -; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|sload ; -; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|clk ; -; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; -; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.457 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y160_N58 ; ; vx_fetch|VX_Warp_zero|real_PC[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1975: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.231 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.233 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.774 ; 86 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.231 ; 3.233 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; -; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; -; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; -; 6.203 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|dataf ; -; 6.231 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|combout ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|d ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X97_Y165_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1976: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.041 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.720 ; 84 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.230 ; 3.232 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.520 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; -; 6.147 ; 0.627 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|datac ; -; 6.230 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|combout ; -; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|d ; -; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|clk ; -; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y165_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1977: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+---------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[4] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.221 ; -; Data Required Time ; 5.579 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.054 ; ; ; ; ; ; -; Data Delay ; 3.223 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.815 ; 87 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; -; 6.221 ; 3.223 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; -; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; -; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; -; 6.193 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|dataf ; -; 6.221 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|combout ; -; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|d ; -; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|clk ; -; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; -+---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1978: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.242 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.244 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.727 ; 84 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.242 ; 3.244 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; -; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; -; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; -; 6.156 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; -; 6.242 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; -; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1979: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.231 ; -; Data Required Time ; 5.589 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.045 ; ; ; ; ; ; -; Data Delay ; 3.233 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.772 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.231 ; 3.233 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.515 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; -; 6.203 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; -; 6.231 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; -; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; -; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1980: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+--------------------------------------------------------+ -; Path Summary ; -+--------------------+-----------------------------------+ -; Property ; Value ; -+--------------------+-----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.248 ; -; Data Required Time ; 5.606 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+-----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.019 ; ; ; ; ; ; -; Data Delay ; 3.256 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.615 ; 80 ; 0.136 ; 0.755 ; -; Cell ; ; 14 ; 0.515 ; 16 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.248 ; 3.256 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; -; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; -; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; -; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; -; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.213 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 5.968 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; -; 5.995 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; -; 6.001 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; -; 6.172 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; -; 6.248 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; -; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+-------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; -; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; -; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; -+---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1981: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.230 ; -; Data Required Time ; 5.588 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.232 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.784 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.230 ; 3.232 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; -; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; -; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; -; 6.203 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; -; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; -; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1982: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.253 ; -; Data Required Time ; 5.611 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.022 ; ; ; ; ; ; -; Data Delay ; 3.255 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.708 ; 83 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.426 ; 13 ; 0.000 ; 0.080 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.253 ; 3.255 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; -; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; -; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; -; 6.173 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; -; 6.253 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; -; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; -; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1983: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[5] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.598 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.773 ; 86 ; 0.120 ; 1.094 ; -; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; -; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; -; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; -; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.334 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; -; 5.363 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; -; 5.367 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; -; 6.211 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; -; 6.240 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; -; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1984: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[14] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.797 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; -; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; -; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.443 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; -; 5.470 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; -; 5.475 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; -; 6.214 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; -; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1985: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[1] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.780 ; 86 ; 0.110 ; 1.094 ; -; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; -; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; -; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; -; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; -; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; -; 6.214 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; -; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1986: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[6] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.237 ; -; Data Required Time ; 5.595 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.239 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.751 ; 85 ; 0.114 ; 1.094 ; -; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; -; 6.237 ; 3.239 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; -; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; -; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; -; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.418 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; -; 5.447 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; -; 5.452 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; -; 6.158 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; -; 6.237 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; -; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; -; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1987: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.224 ; -; Data Required Time ; 5.582 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.052 ; ; ; ; ; ; -; Data Delay ; 3.226 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.812 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.294 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.224 ; 3.226 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.436 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; -; 5.468 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; -; 5.473 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; -; 6.197 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; -; 6.224 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; -; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; -; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1988: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.233 ; -; Data Required Time ; 5.591 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.044 ; ; ; ; ; ; -; Data Delay ; 3.235 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.826 ; 87 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.233 ; 3.235 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; -; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; -; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; -; 6.206 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; -; 6.233 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; -; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; -; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1989: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.247 ; -; Data Required Time ; 5.605 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.249 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.777 ; 85 ; 0.106 ; 1.094 ; -; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.247 ; 3.249 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.430 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; -; 5.459 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; -; 5.464 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; -; 6.160 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; -; 6.247 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; -; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1990: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-----------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+--------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+--------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.235 ; -; Data Required Time ; 5.593 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+--------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.040 ; ; ; ; ; ; -; Data Delay ; 3.237 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.844 ; 88 ; 0.127 ; 1.094 ; -; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.235 ; 3.237 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; -; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 5.375 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; -; 5.406 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; -; 5.410 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; -; 6.208 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; -; 6.235 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; -; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; -; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; -+---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1991: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[22] ; -; To Node ; vx_d_e_reg|csr_address[6] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.192 ; -; Data Required Time ; 5.550 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.113 ; ; ; ; ; ; -; Data Delay ; 3.200 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.675 ; 84 ; 0.128 ; 0.930 ; -; Cell ; ; 12 ; 0.400 ; 13 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; -; 6.192 ; 3.200 ; ; ; ; ; ; data path ; -; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; -; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; -; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; -; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; -; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; -; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; -; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; -; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; -; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; -; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; -; 6.165 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; -; 6.192 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; -; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; -; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; -; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; -; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; -; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1992: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+---------------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+------------------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+------------------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[3] ; -; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.246 ; -; Data Required Time ; 5.604 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.032 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 5 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; -; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.120 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; -; 6.246 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; -; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; -; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; -; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; -; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; -; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; -; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; -; 6.246 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; -; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; -; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; -+---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1993: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.256 ; -; Data Required Time ; 5.614 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.030 ; ; ; ; ; ; -; Data Delay ; 3.258 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.734 ; 84 ; 0.110 ; 1.046 ; -; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.256 ; 3.258 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; -; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; -; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; -; 5.446 ; 0.529 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; -; 5.518 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; -; 5.522 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; -; 6.227 ; 0.705 ; FF ; IC ; 1 ; MLABCELL_X103_Y157_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~811|dataf ; -; 6.256 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X103_Y157_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~811|combout ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11]|d ; -; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; -+---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11]|clk ; -; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; -; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.614 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y157_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1994: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[14] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.110 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.112 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.653 ; 85 ; 0.119 ; 1.144 ; -; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.110 ; 3.112 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; -; 6.110 ; 1.144 ; FF ; IC ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14]|ena ; -; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y160_N38 ; ; vx_f_d_reg|curr_PC[14] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1995: Setup slack is -0.642 (VIOLATED) -=============================================================================== -+------------------------------------------------+ -; Path Summary ; -+--------------------+---------------------------+ -; Property ; Value ; -+--------------------+---------------------------+ -; From Node ; vx_f_d_reg|instruction[2] ; -; To Node ; vx_f_d_reg|curr_PC[8] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.110 ; -; Data Required Time ; 5.468 ; -; Slack ; -0.642 (VIOLATED) ; -+--------------------+---------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.027 ; ; ; ; ; ; -; Data Delay ; 3.112 ; ; ; ; ; ; -; Number of Logic Levels ; ; 4 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 5 ; 2.653 ; 85 ; 0.119 ; 1.144 ; -; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; -; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; -; 6.110 ; 3.112 ; ; ; ; ; ; data path ; -; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; -; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; -; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; -; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; -; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; -; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; -; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; -; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; -; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; -; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; -; 6.110 ; 1.144 ; FF ; IC ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8]|ena ; -; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8] ; -+---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8]|clk ; -; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8] ; -; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.468 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y160_N19 ; ; vx_f_d_reg|curr_PC[8] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1996: Setup slack is -0.641 (VIOLATED) -=============================================================================== -+-------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------+ -; Property ; Value ; -+--------------------+----------------------------+ -; From Node ; vx_f_d_reg|instruction[23] ; -; To Node ; vx_d_e_reg|upper_immed[3] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.189 ; -; Data Required Time ; 5.548 ; -; Slack ; -0.641 (VIOLATED) ; -+--------------------+----------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.075 ; ; ; ; ; ; -; Data Delay ; 3.197 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.619 ; 82 ; 0.115 ; 0.720 ; -; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.126 ; -; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; -; 6.189 ; 3.197 ; ; ; ; ; ; data path ; -; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; -; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; -; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; -; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; -; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; -; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; -; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; -; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; -; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; -; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; -; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; -; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; -; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; -; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; -; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; -; 6.162 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; -; 6.189 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; -; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; -; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; -; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1997: Setup slack is -0.641 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[17] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.641 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.025 ; ; ; ; ; ; -; Data Delay ; 3.248 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.648 ; 82 ; 0.125 ; 0.708 ; -; Cell ; ; 14 ; 0.474 ; 15 ; 0.000 ; 0.091 ; -; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; -; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; -; 6.240 ; 3.248 ; ; ; ; ; ; data path ; -; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; -; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; -; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; -; 3.751 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; -; 3.756 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; -; 3.881 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; -; 3.907 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; -; 3.912 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; -; 4.268 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; -; 4.358 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.363 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.046 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.137 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.143 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.851 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.879 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.885 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.165 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.240 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1998: Setup slack is -0.641 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_d_e_reg|rd[3] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.641 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.582 ; 80 ; 0.118 ; 0.708 ; -; Cell ; ; 14 ; 0.538 ; 17 ; 0.000 ; 0.111 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; -; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; -; 3.902 ; 0.084 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; -; 3.906 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; -; 4.045 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; -; 4.124 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; -; 4.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; -; 4.247 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; -; 4.358 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; -; 4.363 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; -; 5.046 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; -; 5.137 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.143 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.851 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.879 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.885 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.165 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.240 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #1999: Setup slack is -0.641 (VIOLATED) -=============================================================================== -+-------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------+ -; From Node ; vx_f_d_reg|instruction[0] ; -; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.240 ; -; Data Required Time ; 5.599 ; -; Slack ; -0.641 (VIOLATED) ; -+--------------------+----------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.031 ; ; ; ; ; ; -; Data Delay ; 3.242 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.757 ; 85 ; 0.119 ; 0.788 ; -; Cell ; ; 14 ; 0.365 ; 11 ; 0.000 ; 0.089 ; -; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; -; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; -; 6.240 ; 3.242 ; ; ; ; ; ; data path ; -; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; -; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; -; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; -; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; -; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; -; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; -; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; -; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; -; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; -; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; -; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; -; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; -; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; -; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; -; 5.857 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; -; 5.883 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; -; 5.889 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; -; 6.167 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; -; 6.240 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; -; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; -; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; -; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - - -Path #2000: Setup slack is -0.641 (VIOLATED) -=============================================================================== -+-------------------------------------------------------------------------------------------+ -; Path Summary ; -+--------------------+----------------------------------------------------------------------+ -; Property ; Value ; -+--------------------+----------------------------------------------------------------------+ -; From Node ; vx_f_d_reg|instruction[12] ; -; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; Launch Clock ; clk ; -; Latch Clock ; clk ; -; Data Arrival Time ; 6.241 ; -; Data Required Time ; 5.600 ; -; Slack ; -0.641 (VIOLATED) ; -+--------------------+----------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------+ -; Statistics ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -; Setup Relationship ; 2.500 ; ; ; ; ; ; -; Clock Skew ; -0.049 ; ; ; ; ; ; -; Data Delay ; 3.243 ; ; ; ; ; ; -; Number of Logic Levels ; ; 6 ; ; ; ; ; -; Physical Delays ; ; ; ; ; ; ; -; Arrival Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; -; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; -; Data ; ; ; ; ; ; ; -; IC ; ; 6 ; 2.786 ; 86 ; 0.104 ; 1.094 ; -; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; -; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; -; Required Path ; ; ; ; ; ; ; -; Clock ; ; ; ; ; ; ; -; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; -; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; -+------------------------+--------+-------+-------------+------------+-------+-------+ -Note: Negative delays are omitted from totals when calculating percentages - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Arrival Path ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ -; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; -; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; -; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; -; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; -; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; -; 6.241 ; 3.243 ; ; ; ; ; ; data path ; -; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; -; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; -; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; -; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; -; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; -; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; -; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; -; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; -; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; -; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; -; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; -; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; -; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; -; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; -; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; -; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; -; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; -; 6.215 ; 0.741 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; -; 6.241 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; -; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Data Required Path ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ -; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; -; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; -; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; -; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; -; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; -; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; -; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; -; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; -; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; -; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; -; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; -; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; -; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; -+---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ - ----------------------------- -; Extra Fitter Information ; ----------------------------- -HTML report is unavailable in plain text report export. - -